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a
Wideband Voltage
Feedback Amplifier
AD9623*
FEATURES
CONNECTION DIAGRAM
270 MHz Small Signal Bandwidth
190 MHz Large Signal BW (4 V p-p)
High Slew Rate: 2100 V/s
NC # 1
8 NC #
Low Distortion: –64 dB @ 20 MHz
Fast Settling: 15 ns to 0.01%
2.6 nV/Hz Spectral Noise Density
–INPUT 2
+INPUT 3
7 +VS
6 OUTPUT
؎3 V Supply Operation
APPLICATIONS
ADC Input Driver
Differential Amplifiers
IF/RF Amplifiers
Pulse Amplifiers
OProfessional Video
DAC Current-to-Voltage
BBaseband and Video Communications
SActive Filters/lntegrators/Log Amps
OGENERAL DESCRIPTION
The AD9623 is one of a family of very high speed and wide
Lbandwidth amplifiers utilizing a voltage feedback architecture.
EThese amplifiers define a new level of performance for voltage
feedback amplifiers, especially in the categories of large signal
TEbandwidth, slew rate, settling, low distortion, and low noise.
–VS 4
AD9623
5 NC
# OPTIONAL CAPACITOR CB CONNECTED HERE
DECREASES SETTLING TIME (SEE TEXT).
Other members of the AD962X amplifier family are the
AD9621 (G = +1), AD9622 (G = +2), and the AD9624
(G = +6). A separate data sheet is available from Analog
Devices for each model. Each generic device has been designed
for a different minimum stable gain setting, allowing users flex-
ibility in optimizing system performance. Dynamic performance
specifications such as slew rate, settling time, and distortion vary
from model to model. The table below summarizes key perfor-
Proprietary design architectures have resulted in an amplifier
mance attributes for the AD962X family and can be used as a
family that combines the most attractive attributes of both cur-
selection guide.
rent feedback and voltage feedback amplifiers. The AD9623
exhibits extraordinarily accurate and fast pulse response charac- The AD9623 is offered in industrial and military temperature
teristics (8 ns settling to 0.1%) as well as extremely wide small
ranges. Industrial versions are available in plastic DIP, SOIC,
and large signal bandwidth previously found only in current
and cerdip; MIL versions are packaged in cerdips.
feedback amplifiers. When combined with balanced high imped-
ance inputs and low input noise current more common to volt-
age feedback architectures, the AD9623 offers performance not
previously available in a monolithic operational amplifier.
PRODUCT HIGHLIGHTS
1. Wide Large Signal Bandwidth
2. High Slew Rate
3. Fast Settling
*Protected by U.S. Patent 5,150,074 and others pending.
4. Low Distortion
5. Output Short-Circuit Protected
6. Low Intermodulation Distortion of High Frequencies
Parameter
Minimum Stable Gain
Harmonic Distortion (20 MHz)
Large Signal Bandwidth (4 V p-p)
SSBW (0.5 V p-p)
Slew Rate
Rise/Fall Time (0.5 V Step)
Settling Time (to 0.1%/0.01%)
Input Noise (0.1 MHz – 200 MHz)
AD9621
+1
–52
130
350
1200
2.4
7/11
80
AD9622
+2
–66
160
220
1500
1.7
8/14
49
AD9623
+4
–64
190
270
2100
1.6
8/14
36
AD9624
+6
–66
200
300
2200
1.5
8/14
32
Units
V/V
dB
MHz
MHz
V/µs
ns
ns
µV rms
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

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AD9623–SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS (؎VS = ؎5 V, RLOAD = 100 ; AV = +4; RF = 270 , unless otherwise noted)
Parameter
Conditions
Test AD9623AN/AQ/AR
AD9623SQ
Temp Level Min Typ Max Min Typ Max Units
DC SPECIFICATIONS1
Input Offset Voltage
+25°C I
–8 ± 2 +8 –8 ± 2 +8 mV
Full VI
–10
+10 –10
+10 mV
Input Bias Current
+25°C I
6 12
6 12 µA
Full VI
16 16 µA
Bias Current TC
Full V
30
30 nA/°C
Input Offset Current
+25°C I
–2 ± 0.3 +2 –2 ± 0.3 +2 µA
Full VI
–3
+3 –3
+3 µA
Offset Current TC
Full V
2.0
2.0 nA/°C
Input Resistance
Input Capacitance
Common-Mode Range
Common-Mode Rejection Ratio
Open-Loop Gain
Output Voltage Range
OOutput Current
Output Resistance
BFREQUENCY DOMAIN
SBandwidth (–3 dB)
Small Signal
OLarge Signal
LAmplitude of Peaking
Amplitude of Roll-off
EPhase Nonlinearity
T2nd Harmonic Distortion
E3rd Harmonic Distortion
VCM = 1 V
VOUT = ± 2 V p-p
+25°C
+25°C
Full
+25°C
+25°C
Full
Full
+25°C
V
V
VI
I
V
VI
VI
V
VOUT = 0.4 V p-p
VOUT = 4 V p-p
Full Spectrum
DC to 100 MHz
0.3 to 100 MHz
2 V p-p; 20 MHz
2 V p-p; 20 MHz
Full
+25°C
Full
Full
+25°C
Full
Full
II
V
II
II
V
II
II
600
1.2
± 3.0 ± 3.4
52 63
69
± 3.0 ± 3.4
60 70
0.3
600
1.2
± 3.0 ± 3.4
52 63
69
± 3.0 ± 3.4
60 70
0.3
k
pF
V
dB
dB
V
mA
190 270
190 270
MHz
190 190 MHz
0.1 1.2
0.1 1.2 dB
0 0.7
0 0.7 dB
1.0 1.0 Degree
–64 –56
–64 –56 dBc
–72 –65
–72 –65 dBc
Common-Mode Rejection Ratio @ 20 MHz
+25°C V
+21
+21 dB
Spectral Input Noise Voltage
1 to 200 MHz
+25°C V
2.6
2.6 nV/Hz
Spectral Input Noise Current
1 to 200 MHz
+25°C V
2.5
2.5 pA/Hz
Average Equivalent Integrated
Input Noise Voltage
0.1 to 200 MHz +25°C V
36
36 µV rms
TIME DOMAIN
Slew Rate
Rise/Fall Time
Overshoot
Settling Time
To 0.1%
To 0.01%
To 0.1%2
To 0.01%2
Overdrive Recovery
Differential Gain (4.3 MHz)
Differential Phase (4.3 MHz)
VOUT = 5 V Step
VOUT = 0.5 V Step
VOUT = 5 V Step
VOUT = 2 V Step
Full
+25°C
Full
Full
IV
V
VI
IV
VOUT = 2 V Step
VOUT = 2 V Step
VOUT = 4 V Step
VOUT = 4 V Step
2ϫ to ± 2 mV
RL = 150
RL = 150
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
V
IV
V
V
V
V
V
POWER SUPPLY REQUIREMENTS1
Supply Voltage (± VS)
Quiescent Current
+IS
–IS
Power Supply Rejection Ratio
+VS = +5 V
–VS = –5 V
VS = 1 V
Full IV
Full VI
Full VI
+25°C I
NOTES
1Measured at AV = 21.
2Measured with a 0.001 µF CB capacitor connected across Pins 1 and 8.
Specifications subject to change without notice.
1500
2100
1.6
2.4 3.1
3 15
8
15 20
9
17
150
0.01
<0.01
1500
2100
1.6
2.4 3.1
3 15
V/µs
ns
ns
%
8
15 20
9
17
150
0.01
<0.01
ns
ns
ns
ns
ns
%
Degree
3.0 5.0 5.5 3.0 5.0 5.5 V
23 29
23 29 mA
23 29
23 29 mA
60 71
60 71
dB
–2– REV. 0

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AD9623
ABSOLUTE MAXIMUM RATINGS1
THEORY OF OPERATION
Supply Voltages (± VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V The AD9623 is a wide bandwidth voltage feedback amplifier
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± VS that is guaranteed for minimum gain stability of +4. Since its
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V open-loop frequency response follows the conventional 6 dB/
Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . . 90 mA octave roll-off, its gain bandwidth product is basically constant.
Operating Temperature Ranges
Increasing its closed-loop gain results in a corresponding de-
AN, AQ, AR . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C crease in small signal bandwidth. The AD9623 typically main-
SQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C tains a 60 degree unity loop gain phase margin. This high
Storage Temperature
margin minimizes the effects of signal and noise peaking.
Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Feedback Resistor Choice
Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C At minimum stable gain (+4), the AD9623 provides optimum
Junction Temperature
Ceramic3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Soldering Temperature (1 minute)4 . . . . . . . . . . +220°C
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
O2Output is short-circuit protected; for maximum reliability, 90 mA continuous
current should not be exceeded.
3Typical thermal impedances (part soldered onto board; no air flow):
BCeramic DIP: θJA = 100°C/W; θJC = 30°C/W
Plastic SOIC: θJA = 125°C/W; θJC = 45°C/W
SPlastic DIP: θJA = 90°C/W; θJC = 45°C/W
4Temperature shown is for surface mount devices, mounted by vapor phase
Osoldering. Throughhole devices (ceramic and plastic DIPs) can be soldered at
+300°C for 10 seconds.
LORDERING GUIDE
ETEModel
Temperature
Range
Package
Description
Package
Option
dynamic performance with RF 390 . When using this value
and following the high speed layout guidelines, a shunt capacitor
(CF) should not be required. This value for RF provides the best
combination of wide bandwidth, low peaking, and distortion.
However, if improved gain flatness is desired, a shunt capacitor
(CF) will provide extra phase margin. This reduces both over-
shoot and peaking with only a slight reduction of bandwidth.
See Figure 1.
As an example, if the amplifier exhibits (worst case) peaking of
1 dB with RGʈRF = 98 (AV = 4), then using an effective CF of
0.5–1 pF across RF will reduce this peaking to 0 dB. In addition,
overshoot, noise, and settling time (0.01%) will also improve.
This comes at the expense of slightly decreased closed-loop
bandwidth due to the RF ϫ CF time constant created.
If total input capacitance greatly exceeds 3 pF (due to source
drive or long input traces to the amplifier), then added shunt
capacitance (CF) will be necessary to maintain stability for
minimum gain.
AD9623AN
AD9623AQ
AD9623AR
AD9623SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
8-Pin Plastic DIP
8-Pin Cerdip
8-Pin SOIC
8-Pin Cerdip
N-8
Q-8
R-8
Q-8
Likewise, if larger RG/RF minimum-gain setting resistors are
used, CF will be necessary. As a rule of thumb, if the product of
RFʈRG ϫ CI 300 ϫ 10–12 seconds, then CF is not required (for
maximum bandwidth at minimum gain) and the amplifier’s
phase margin will maintain about 60°.
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures. AC testing of “A” grade devices
done on sample basis.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
+VS
CB+
CB–
OUTPUT
– INPUT
46.5mm
54mils
–VS
For RFʈRG >150 , use a CF equal to CI ϫ RG/RF. For CI
(total) @ 2 pF, requires CF to be 0.5 pF. This can be achieved
by two 1 pF capacitors in series, or by using a resistor divider
network at the amplifier’s output in conjunction with a larger
capacitor. Increasing CF much beyond these guidelines will also
cause amplifier instability.
Pulse Response
Unlike a traditional voltage feedback amplifier in which slew
speed is usually dictated by its front end dc quiescent current
and gain bandwidth product, the AD9623 provides “on de-
mand” transconductance current that increases proportionally
to the input “step” signal amplitude. This results in slew speeds
(2100 V/µs) comparable to wideband current feedback designs.
This, combined with relatively low input noise current
(2.5 pA/Hz), gives the AD9623 the best attributes of both volt-
age and current feedback amplifiers.
Bootstrap Capacitor (CB)
In most applications, the CB capacitor should not be required.
Under certain conditions, it can be used to further enhance set-
tling time performance.
–INPUT +INPUT
46.5mils
Chip Layout
REV. 0
–3–

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AD9623
+VS
6.8µF
+VS
6.8µF
0.1µF
0.1µF
RF RG
7
7
38
CB (OPTIONAL)
VIN
38
CB (OPTIONAL)
6 VOUT
6 VOUT
2
1
CF
2
1
CF
RF
RG
VIN
4
4
0.1µF
RF
0.1µF
RF
500
RG 500
CF
CI
VOUT
Figure 1. Transimpedance
Configuration
6.8µF
AV
=
–RF
RG
–VS
Figure 2. Inverting Gain Connection
Diagram
6.8µF
AV = 1+
RF
RG
–VS
Figure 3. Noninverting Gain Connection
Diagram
OBSThe CB capacitor (0.001 µF) connects to the internal high im-
pedance nodes of the amplifier. Using this capacitor will reduce
Othe large signal (4 V) step output settling time by 3 ns to 5 ns
for 0.05% or greater accuracy. For settling accuracy less than
L0.05% or for smaller step sizes, its effect will be less apparent.
EUnder heavy slew conditions, this capacitor forces the internal
Tsignal (initial step) amplitude to be controlled by the “on”
E(slewed) transistor, preventing its complement from completely
Layout Considerations
As with all wide bandwidth components, printed circuit layout
is critical to obtain best dynamic performance with the AD9623.
The ground plane in the area of the amplifier and its associated
components should cover as much of the component side of the
board as possible (or first interior layer of a multilayer surface
mount board).
The ground plane should be removed in the area of the inputs
turning off. This allows for faster settling time of these (internal)
nodes and thus, the output also.
In the frequency domain, total (high frequency) distortion will
be approximately the same with or without CB. Typically, the
3rd harmonic will be greater than the 2nd without CB. This will
be reversed with CB in place.
and RF and RG to minimize stray capacitance at the input. The
same precaution should be used for CB, if used. Each power
supply trace should be decoupled close to the package with a
0.1 µF ceramic capacitor, plus a 6.8 µF tantalum nearby.
All lead lengths for input, output, and feedback resistor should
be kept as short as possible. All gain setting resistors should be
chosen for low values of parasitic capacitance and inductance,
APPLICATIONS
i.e., microwave resistors and/or carbon resistors.
The AD9623 is a voltage feedback amplifier and is well suited
for such applications as active filters, and log amplifiers. The
device’s wide bandwidth (270 MHz), phase margin (60°), low
noise current (2.6 pA /Hz), and slew rate (2100 V/µs) give
higher performance capabilities to these applications over previ-
ous voltage feedback designs.
Microstrip techniques should be used for lead lengths in excess
of one inch. Sockets should be avoided if at all possible because
of their high series inductance. If sockets are necessary, indi-
vidual pin sockets such as AMP p/n 6-330808-3 should be used.
These contribute far less stray reactance than molded socket
assemblies.
Its settling time of 15 ns to 0.01% and 8 ns to 0.1%, and its low
harmonic distortion make it a good for choice for ADC signal
amplification. With superb linearity at relatively high signal fre-
An evaluation board is available from Analog Devices for a
nominal charge.
quencies, it is an ideal driver for ADCs up to 14 bits.
–4– REV. 0

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Typical Performance (RL = 100 ; AV = +4, unless otherwise noted) AD9623
80
GAIN
+90 +2
+75
+180
+135
+2
+180
+135
60
PHASE
40
+60 0
+45
+30 –2
+15
AV = –3
+90
+45
0
–45
0 +90
AV = 6
–2
+45
0
AV = 4
–45
20 0 –4 –90 –4 –90
–15 –135
–135
0
–20
10k
100k 1M 10M 100M
FREQUENCY – Hz
–30
–45
–60
600M
–6
AV = –6
–180
–8
50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
–6
AV = 6,12
AV = 12
–180
–8
50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
Figure 4. Open-Loop Gain and Phase
Figure 5. Inverting Frequency
Figure 6. Noninverting Frequency
–50
VOUT = 2Vp-p
–60
2nd HARMONIC
RL = 100
–70
O–80 2nd HARMONIC
RL = 500
B–90
S–100
O–110
3rd HARMONIC
RL = 100
3rd HARMONIC
RL = 500
L–120
1
2
4 6 10
20 40 60
FREQUENCY – MHz
EFigure 7. Harmonic Distortion
TEvs. Frequency
Response
50
40
30
5500
OUT
50
20
10
1 10 100
FREQUENCY – MHz
Figure 8. Third Order Intercept
Response
+20
+25
+30
+35
+40
+45
+50
+55
+60 CMRR
+65
+70
1
PSRR
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY – Hz
Figure 9. CMRR and PSRR vs.
Frequency
+2
+180
+0.1
+0.1
AV = 4
RFB = 390
+135
+0.08
TEST CIRCUIT
+0.08
VOUT = 2V STEP
0
RFF = 130
+90
+0.06
100
6pF
+0.06
+45 +0.04
–2
RLOAD = 5000
+0.02
+0.04
+0.02
–45 0
0
–4
–6
RLOAD = 50
–90
–135
–180
–0.02
–0.04
–0.06
–0.08
VOUT = 2V STEP
–0.02
–0.04
–0.06
–0.08
TEST CIRCUIT
100
6pF
–8
50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
Figure 10. Frequency Response
vs. RLOAD
–0.1
0 10 20 30 40 50
TIME – ns
Figure 11. Short-Term Settling Time
–0.1
1
10 100 1K 10K 100K
TIME – ns
Figure 12. Long-Term Settling Time
10 10
88
66
44
CURRENT
2
VOLTAGE
2
1102
103 104 105
FREQUENCY – Hz
106 1
Figure 13. Input Spectral Noise
Density
27 4
VOLTAGE
23 3
CURRENT
19 2
3.5 4.0 4.5 5.0
SUPPLY VOLTAGE – ±Volts
5.5
Figure 14. Output Level and Sup-
ply Current vs. Supply Voltage
30 30
26
RS
22 1k CL
390
130
RS
18
tSETTLING
14
26
22
18
14
10 10
1 10 100
CLOAD – pF
Figure 15. Settling Time vs.
Capacitive Load
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–5–