74HC573.pdf 데이터시트 (총 20 페이지) - 파일 다운로드 74HC573 데이타시트 다운로드

No Preview Available !

74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Rev. 7 — 4 March 2016
Product data sheet
1. General description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The
device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data
at the inputs enter the latches. In this condition the latches are transparent, a latch output
will change each time its corresponding D-input changes. When LE is LOW the latches
store the information that was present at the inputs a set-up time preceding the
HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches. Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
2. Features and benefits
Input levels:
For 74HC573: CMOS level
For 74HCT573: TTL level
Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Multiple package options
Complies with JEDEC standard no. 7 A
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C

No Preview Available !

NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74HC573D 40 C to +125 C
74HCT573D
74HC573DB 40 C to +125 C
74HCT573DB
74HC573PW 40 C to +125 C
74HCT573PW
74HC573BQ 40 C to +125 C
74HCT573BQ
Name
SO20
SSOP20
TSSOP20
DHVQFN20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
4. Functional diagram
 '
 '
 '
 '
 '
 '
 '
 '
 /(
 2(
Fig 1. Functional diagram
/$7&+
WR
67$7(
2873876
4 
4 
4 
4 
4 
4 
4 
4 
PQD
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 20

No Preview Available !

NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
' ' ' ' ' ' ' '
'4
'4
'4
'4
'4
'4
'4
'4
/$7&+

/(
/$7&+

/(
/$7&+

/(
/$7&+

/(
/$7&+

/(
/$7&+

/(
/$7&+

/(
/$7&+

/(
/(
2(
4 4 4 4 4 4 4 4
DDH
Fig 2. Logic diagram


2(
' 4

 '
4 
 '
4 
 '
4 
 '
4 
 '
4 
 '
4 
 '
4 
/(
 PQD
Fig 3. Logic symbol
 &
 (1
 '















PQD
Fig 4. IEC logic symbol
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 20

No Preview Available !

NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
2( 
' 
' 
' 
' 
' 
' 
' 
' 
*1' 
+&
+&7
 9&&
 4
 4
 4
 4
 4
 4
 4
 4
 /(
DDH
Fig 5. Pin configuration SO20, SSOP20 and
TSSOP20
WHUPLQDO
LQGH[DUHD
+&
+&7
' 
' 
' 
' 
' 
' 
' 
' 
*1' 
 4
 4
 4
 4
 4
 4
 4
 4
DDH
7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
D[0:7]
GND
LE
Q[0:7]
VCC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
latch enable input (active HIGH)
3-state latch output
supply voltage
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 20

No Preview Available !

NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Enable and read register (transparent
mode)
Latch and read register
Latch register and disable outputs
Control
OE
L
L
H
LE
H
L
L
Input
Dn
L
H
l
h
l
h
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
7. Limiting values
Internal
latches
L
H
L
H
L
H
Output
Qn
L
H
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
SO20, SSOP20, TSSOP20 and DHVQFN20
packages
0.5
-
-
-
-
70
65
[1] -
+7
20
20
35
+70
-
+150
500
V
mA
mA
mA
mA
mA
C
mW
[1] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 20