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CS3842B/CS3843B
Off-Line Current Mode PWM Control Circuit
with Very Low Start Up Current
Description
Features
The CS384XB provides all the neces-
sary features to implement off-line
fixed frequency current-mode control
with a minimum number of external
components. The family has been opti-
mized for very low start up current
(300µA, typ).
The CS384XB family incorporates a
precision temperature-controlled oscil-
lator with an internally trimmed dis-
charge current to minimize variations
in frequency. A precision duty-cycle
clamp eliminates the need for an exter-
nal oscillator when a 50% duty-cycle is
used. Duty-cycles of almost 100% are
possible. On board logic ensures that
VREF is stabilized before the output
stage is enabled. Ion-implant resistors
provide tighter control of undervoltage
lockout.
Other features include pulse-by-pulse
current limiting, and a high-current
totem pole output for driving capaci-
tive loads, such as the gate of a power
MOSFET. The output is LOW in the off
state, consistent with N-channel
devices.
These ICs are available in 8 and 14 lead
surface mount (SO) and 8 lead PDIP
packages.
Absolute Maximum Ratings
Supply Voltage (ICC<30mA) ..........................................................Self Limiting
Supply Voltage (Low Impedance Source)...................................................30V
Output Current ...............................................................................................±1A
Output Energy (Capacitive Load) .................................................................5µJ
Analog Inputs (VFB, Sense) ............................................................-0.3V to 5.5V
Error Amp Output Sink Current...............................................................10mA
Lead Temperature Soldering
Wave Solder (through hole styles only) ...................10 sec. max, 260°C peak
Reflow (SMD styles only) ....................60 sec. max above 183°C, 230°C peak
Block Diagram
VCC
Gnd
OSC
VFB
COMP
Sense
34V
Undervoltage
Lock-out Circuit
Set/
5V
Reset Reference
16V/10V
(8.4V/7.6V)
REF 2.50V
Output
Enable
Oscillator
Internal
Bias
NOR
+
Error
VC
Amplifier
2R
R
S
R
1 V Current
Sense
Comparator
PWM
Latch
( ) Indicates CS-3843B
VCC Pwr
VREF
V O UT
Pwr Gnd
s Very low Start Up Current
(300µA typ)
s Optimized Off-line
Control
s Internally Trimmed,
Temperature
Compensated Oscillator
s Maximum Duty-cycle
Clamp
s OVRuEtFpsuttabEinlaizbalteion before
s Pulse-by-pulse Current
Limiting
s Improved Undervoltage
Lockout
s Double Pulse Suppression
s 1% Trimmed Bandgap
Reference
s High Current Totem Pole
Output
Package Options
8 Lead PDIP & SO Narrow
COMP 1
VFB 2
Sense 3
OSC 4
8 VREF
7 VCC
6 VOUT
5 Gnd
14L SO Narrow
COMP 1
NC 2
VFB 3
NC 4
Sense 5
NC 6
OSC 7
14 VREF
13 NC
12 VCC
11 VCC Pwr
10 VOUT
9 Pwr Gnd
8 Gnd
Rev. 6/23/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
1 A ® Company

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Electrical Characteristics: 0TA70˚C, VCC=15V (Note 1); RT=680, CT=.022µF for triangular mode,
RT=10k, CT=3.3nF for sawtooth mode (see Fig. 3), unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
s Reference Section
Output Voltage
Line Regulation
Load Regulation
Temperature Stability
Total Output Variation
Output Noise Voltage
Long Term Stability
Output Short Circuit
TJ=25˚C, IOUT=1mA
12VIN25V
1IOUT20mA
(Note 2)
Line, Load, Temperature (Note 2)
10Hzf10kHz, TJ=25˚C (Note 2)
TA=125˚C, 1kHrs. (Note 2)
TA=25˚C
4.90 5.00
6
6
0.2
4.82
50
5
-30 -100
5.10
20
25
0.4
5.18
25
-180
s Oscillator Section
Initial Accuracy
Voltage Stability
Temp. Stability
Amplitude
Discharge Current
Sawtooth Mode (see Fig. 3), TJ=25˚C
Triangular Mode (see Fig. 3), TJ=25˚C
12VCC25V
Sawtooth Mode TMINTATMAX
(Note 2)
Triangular Mode TMINTATMAX
(Note 2)
Oscillator peak to peak
TJ=25˚C
TMINTATMAX
47 52
44 52
0.2
5
8
1.7
7.5 8.3
7.2
57
60
1.0
9.3
9.5
s Error Amp Section
Input Voltage
Input Bias Current
AVOL
Unity Gain Bandwidth
PSRR
Output Sink Current
Output Source Current
VOUT High
VOUT Low
VCOMP=2.5V
2VOUT4V
(Note 2)
12VCC25V
VFB=2.7V, VOSC=1.1V
VFB=2.3V, VOSC=5V
VFB=2.3V, RL=15kto ground
VFB=2.7V, RL=15kto VREF
2.42 2.50
-0.3
65 90
0.7 1.0
60 70
26
-0.5 -0.8
56
0.7
2.58
-2.0
1.1
s Current Sense Section
Gain
Maximum Input Signal
PSRR
Input Bias Current
Delay to Output
(Notes 3 & 4)
VCOMP=5V (Note 3)
12VCC25V (Note 3)
TJ=25˚C (Note 2)
2.85 3.00
0.9 1.0
70
-2
150
3.15
1.1
-10
300
s Output Section
Output Low Level
Output High Level
ISINK=20mA
ISINK=200mA
ISOURCE=20mA
ISOURCE=200mA
0.1
1.5
13.0 13.5
12.0 13.5
0.4
2.2
UNITS
V
mV
mV
mV/˚C
V
µV
mV
mA
kHz
kHz
%
%
%
V
mA
mA
V
µA
dB
MHz
dB
mA
mA
V
V
V/V
V
dB
µA
ns
V
V
V
V
2

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PARAMETER
s Output Section: continued
Rise Time
Fall Time
Output Leakage
Electrical Characteristics: continued
TEST CONDITIONS
MIN
TJ=25˚C, CL=1nF (Note 2)
TJ=25˚C, CL=1nF (Note 2)
UVLO Active, VOUT=0
s Total Standby Current
Start-Up Current
Operating Supply Current
VCC Zener Voltage
VFB=VSense=0V RT=10k, CT=3.3nF
ICC=25mA
TYP
50
50
-0.01
0.3
11
34
MAX
UNITS
150
150
-10.00
ns
ns
µA
0.5 mA
17 mA
V
PARAMETER
TEST CONDITIONS
s Under-Voltage Lockout Section
Start Threshold
Min. Operating
Voltage
After Turn On
Notes: 1. Adjust VCC above the start threshold before setting at 15V.
2. These parameters, although guaranteed, are not 100% tested
in production.
CS-3842B
CS-3843B
MIN TYP MAX MIN TYP MAX UNITS
14.5 16.0 17.5
8.5 10.0 11.5
7.8
7.0
8.4 9.0
7.6 8.2
V
V
3. Parameter measured at trip point of latch with VFB=0.
4. Gain defined as:
A=
VCOMP
VSense
; 0 VSense 0.8V.
PACKAGE PIN #
8L PDIP/SO 14L SO Narrow
11
23
35
47
58
9
6 10
11
7 12
8 14
2,4,6,13
Package Pin Description
PIN SYMBOL
FUNCTION
COMP
VFB
Sense
OSC
Gnd
Pwr Gnd
VOUT
VCCPwr
VCC
VREF
NC
Error amp output, used to compensate error amplifier
Error amp inverting input
Noninverting input to Current Sense Comparator
Oscillator Timing Network with Capacitor to Ground, resistor
to VREF
Ground
Output driver Ground
Output drive pin
Output driver positive supply
Positive power supply
Output of 5V internal reference
No Connection
3

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Typical Performance Characteristics:
Oscillator Frequency vs CT
Oscillator Duty Cycle vs RT
900
800
RT =680
700
600
500
RT =1.5k
400
300
200
RT =10k
100
.0005
.001
.002 .003 .005
CT (µF)
.01
.02 .03 .04 .05
100
90
80
70
60
50
40
30
20
10
100 200 300 400 500 700 1k
2k 3k 4k 5k 7k 10k
RT ()
Test Circuit
4.7k
RT
2N2222
100k
COMP
VREF
1k
ERROR AMP
ADJUST
4.7k
5k
Sense
ADJUST
CS-3842B
VFB CS-3843B VCC
Sense
V O UT
OSC
Gnd
0.1µF
A
0.1µF
1k
1W
VREF
VCC
V O UT
CT
Circuit Description
Gnd
VCC
ON/OFF Command
to reset of IC
VON
VOFF
CS3842B CS3843B
16V
10V
8.4V
7.6V
ICC
<15mA
<0.5mA
VON VOFF
Figure 1: Typical Undervoltage Characteristics
VCC
Undervoltage Lockout
During Undervoltage Lockout (Figure 1), the output driv-
er is biased to a high impedance state. VOUT should be
shunted to ground with a resistor to prevent output leak-
age current from activating the power switch.
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current
(Figure 2). An increase in VCC causes the inductor current
slope to increase, thus reducing the duty cycle. This is an
inherent feed-forward characteristic of current mode con-
trol, since the control voltage does not have to change
during changes of input supply voltage.
When the power supply sees a sudden large output cur-
rent increase, the control voltage will increase allowing
the duty cycle to momentarily increase. Since the duty
4

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VOSC
OSC
RESET
EA Output
Switch
Current
VCC
IOUT
VOUT
Figure 2: Timing Diagram for key CS-384XB parameters
Figure 3: Oscillator
cycle tends to exceed the maximum allowed, to prevent
transformer saturation in some power supplies, the inter-
nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
Setting the Oscillator
The oscillator timing capacitor, CT, is charged by VREF
through RT and discharged by an internal current source
(Figure 3). During the discharge time, the internal clock
signal blanks out the output to the Low state, thus provid-
ing a user selected maximum duty cycle clamp.
Charge and discharge times are determined by the general
formulas:
( )tc = RTCT ln
VREF – Vlower
VREF – Vupper
( )td = RTCT ln
VREF – Id RT –Vlower
VREF – Id RT – Vupper
VREF
OSC
Gnd
RT
CT
Vupper
Vlower
tc
Sawtooth Mode
LARGE RT (10k)
td
VOSC
Triangular Mode
SMALL RT (700k)
Internal Clock
VREF
Substituting in typical values for the parameters in the
above formulas:
VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA,
then
tc 0.5534RTCT
( )td = RTCT ln
2.3 – 0.0083 RT
4.0 – 0.0083 RT
The frequency and maximum duty cycle can be deter-
mined from the Typical Performance Characteristics
graphs.
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to ground in a single
point ground.
The transistor and 5kpotentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
Internal Clock
Figure 3: Oscillator Timing Network and parameters
5