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CS4205
CrystalClear® Audio Codec ’97 for Portable Computing
Features
! Integrated Asynchronous I2S Input Port
(ZV Port)
! Integrated High-Performance Microphone
Pre-Amplifier
! Integrated Digital Effects Processing for Bass
and Treble Response
! Digital Docking Including an I2S Output, 3
Synchronous I2S Inputs
! Performance Oriented Digital Mixer
! SRS© 3D Stereo Enhancement
! On-chip PLL for use with External Clock
Sources
! Dedicated Microphone Analog-to-Digital
Converter
! Sample Rate Converters
! S/PDIF Digital Audio Output
! AC ’97 2.1 Compliant
! PC Beep Bypass
! 20-bit Stereo Digital-to-Analog Converters
! 18-bit Stereo Analog-to-Digital Converters
! Three Analog Line-level Stereo Inputs for
LINE IN, VIDEO, and AUX
! High Quality Pseudo-Differential CD Input
! Extensive Power Management Support
! Meets or Exceeds the Microsoft® PC 99 and
PC 2001 Audio Performance Requirements
Description
The CS4205 is an AC ’97 2.1 compliant stereo audio co-
dec designed for PC multimedia systems. It uses
industry leading CrystalClear® delta-sigma and mixed
signal technology. The CS405 is the first Cirrus AC ’97
audio codec to feature digital centric mixing and digital
effects. This advanced technology and these features
are designed to help enable the design of PC 99 and
PC 2001 compliant high-quality audio systems for desk-
top, portable, and entertainment PCs.
Coupling the CS4205 with a PCI audio accelerator or
core logic supporting the AC ’97 interface implements a
cost effective, superior quality audio solution. The
CS4205 surpasses PC 99, PC 2001, and AC ’97 2.1 au-
dio quality standards.
ORDERING INFO
CS4205-KQZ, Lead Free 48-pin TQFP 9x9x1.4 mm
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
ID0#
ID1#
GPIO0/LRCLK
GPIO1/SDOUT
EAPD/SCLK
SPDO/SDO2
GPIO[2:4]/SDI[1:3]
ZSCLK,ZSDATA,ZLRCLK
AC-LINK AND AC '97
REGISTERS
TEST
PWR
MGT
AC-
LINK
AC
'97
REG
SIGNAL
PROCESSING
ENGINE
ANALOG INPUT MUX
AND OUTPUT MIXER
SRC PCM_DATA
SRC MIC_PCM_DATA
GAIN / MUTE CONTROLS
MIXER / MUX SELECTS
18 bit
ADC
(2ch)
18 bit
ADC
(1ch)
INPUT
MUX
INPUT
MIXER
Σ
GPIO
S/PDIF
SERIAL DATA PORT
ZV PORT
OUTPUT
MIXER
Σ20 bit
SRC PCM_DATA DAC
(2ch)
LINE
CD
AUX
VIDEO
MIC1
MIC2
PHONE
PC_BEEP
LINE_OUT
MONO_OUT
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
JULY '05
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CS4205
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 6
ANALOG CHARACTERISTICS ................................................................................................ 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7
RECOMMENDED OPERATING CONDITIONS ....................................................................... 7
AC ’97 SERIAL PORT TIMING................................................................................................. 9
2. GENERAL DESCRIPTION ..................................................................................................... 12
2.1 AC-Link ............................................................................................................................ 12
2.2 Control Registers ............................................................................................................. 13
2.3 Sample Rate Converters .................................................................................................. 13
2.4 Mixers .............................................................................................................................. 13
2.5 Input Mux ......................................................................................................................... 13
2.6 Volume Control ................................................................................................................ 13
2.7 Dedicated Mic Record Path ............................................................................................. 13
3. DIGITAL SIGNAL PATHS ...................................................................................................... 15
3.1 Analog Centric Mode ....................................................................................................... 15
3.2 Digital Centric Mode ......................................................................................................... 16
3.3 Host Processing Mode ..................................................................................................... 16
3.4 Multi-Channel Mode ......................................................................................................... 16
4. AC-LINK FRAME DEFINITION .............................................................................................. 18
4.1 AC-Link Serial Data Output Frame .................................................................................. 19
4.1.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 19
4.1.2 Command Address Port (Slot 1) .................................................................................... 19
4.1.3 Command Data Port (Slot 2).......................................................................................... 20
4.1.4 PCM Playback Data (Slots 3-11) ................................................................................... 20
4.1.5 GPIO Pin Control (Slot12).............................................................................................. 20
4.2 AC-Link Serial Data Input Frame ..................................................................................... 21
4.2.1 Serial Data Input Slot Tag Bits (Slot 0) ........................................................................ 21
4.2.2 Status Address Port (Slot 1) .......................................................................................... 21
4.2.3 Status Data Port (Slot 2) ................................................................................................ 22
4.2.4 PCM Capture Data (Slot 3-8,11).................................................................................... 22
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to
verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for
the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of
third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here-
in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of
Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED
FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SE-
CURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS
IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IM-
PLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS
PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PROD-
UCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES,
DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR
ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
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4.2.5 GPIO Pin Status (Slot 12) ............................................................................................. 22
4.3 AC-Link Protocol Violation - Loss of SYNC ..................................................................... 23
5. REGISTER INTERFACE .................................................................................................... 24
5.1 Reset Register (Index 00h) .............................................................................................. 26
5.2 Master Volume Register (Index 02h) ............................................................................... 26
5.3 Mono Volume Register (Index 06h) .................................................................................. 28
5.4 Master Tone Control Register (Index 08h) ....................................................................... 28
5.5 PC_BEEP Volume Register (Index 0Ah) .......................................................................... 29
5.6 Phone Volume Register (Index 0Ch) ................................................................................ 29
5.7 Microphone Volume Register (Index 0Eh)........................................................................ 30
5.8 Analog Mixer Input Gain Registers (Index 10h - 18h) ...................................................... 31
5.9 Input Mux Select Register (Index 1Ah) ............................................................................. 32
5.10 Record Gain Register (Index 1Ch) ................................................................................. 33
5.11 Record Gain Mic Register (Index 1Eh) ........................................................................... 33
5.12 General Purpose Register (Index 20h) ......................................................................... 34
5.13 3D Control Register (Index 22h) ..................................................................................... 34
5.14 Powerdown Control/Status Register (Index 26h) ........................................................... 35
5.15 Extended Audio ID Register (Index 28h) ........................................................................ 36
5.16 Extended Audio Status/Control Register (Index 2Ah) .................................................... 37
5.17 Audio Sample Rate Control Registers (Index 2Ch - 34h) ............................................... 38
5.18 Extended Modem ID Register (Index 3Ch) .................................................................... 39
5.19 Extended Modem Status/Control Register (Index 3Eh) ................................................. 39
5.20 GPIO Pin Configuration Register (Index 4Ch) ................................................................ 39
5.21 GPIO Pin Polarity/Type Configuration Register (Index 4Eh) .......................................... 40
5.22 GPIO Pin Sticky Register (Index 50h) ............................................................................ 40
5.23 GPIO Pin Wakeup Mask Register (Index 52h) ............................................................... 41
5.24 GPIO Pin Status Register (Index 54h)............................................................................ 41
5.25 AC Mode Control Register (Index 5Eh) .......................................................................... 41
5.26 Misc. Crystal Control Register (Index 60h) ..................................................................... 44
5.27 S/PDIF Control Register (Index 68h) .............................................................................. 45
5.28 Serial Port Control Register (Index 6Ah) ........................................................................ 46
5.29 Special Feature Address Register (Index 6Ch) .............................................................. 47
5.30 Special Feature Data Register (Index 6Eh) ................................................................... 47
5.31 Digital Mixer Input Volume Registers (Index 6Eh, Address 00h - 05h) .......................... 47
5.32 Serial Data Port Volume Control Registers (Index 6Eh, Address 06h - 07h) ................. 48
5.33 Signal Processing Engine Control Register (Index 6Eh, Address 08h) .......................... 49
5.34 Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh) ....... 50
5.35 BIOS-Driver Interface Control Registers (Index 6Eh, Address 0Ch - 0Dh) .................... 51
5.36 ZV Port Control/Status Registers (Index 6Eh, Address 0Eh - 0Fh) ................................ 51
5.37 BIOS-Driver Interface Status Register (Index 7Ah) ........................................................ 51
5.38 Vendor ID1 Register (Index 7Ch) ................................................................................... 53
5.39 Vendor ID2 Register (Index 7Eh) ................................................................................... 53
6. SERIAL DATA PORTS ........................................................................................................... 54
6.1 Overview .......................................................................................................................... 54
6.2 Multi-Channel Expansion ................................................................................................. 54
6.3 Digital Docking ................................................................................................................. 55
6.4 Serial Data Formats ......................................................................................................... 55
7. ZV PORT ................................................................................................................................. 57
8. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 58
9. EXCLUSIVE FUNCTIONS ...................................................................................................... 58
10. POWER MANAGEMENT ..................................................................................................... 59
10.1 AC ’97 Reset Modes ...................................................................................................... 59
10.1.1 Cold Reset ........................................................................................................ 59
10.1.2 Warm Reset ...................................................................................................... 59
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10.1.3 New Warm Reset .............................................................................................. 59
10.1.4 Register Reset .................................................................................................. 59
10.2 Powerdown Controls ...................................................................................................... 60
11. CLOCKING ........................................................................................................................... 62
11.1 PLL Operation (External Clock) ..................................................................................... 62
11.2 24.576 MHz Crystal Operation ....................................................................................... 62
11.3 Secondary Codec Operation .......................................................................................... 62
12. ANALOG HARDWARE DESCRIPTION ............................................................................... 64
12.1 Analog Inputs ................................................................................................................. 64
12.1.1 Line Inputs ......................................................................................................... 64
12.1.2 CD Input ............................................................................................................ 64
12.1.3 Microphone Inputs ............................................................................................. 65
12.1.4 PC Beep Input ................................................................................................... 65
12.1.5 Phone Input ....................................................................................................... 65
12.2 Analog Outputs .............................................................................................................. 65
12.2.1 Stereo Output .................................................................................................... 66
12.2.2 Mono Output ..................................................................................................... 66
12.3 Miscellaneous Analog Signals ....................................................................................... 66
12.4 Power Supplies .............................................................................................................. 66
12.5 Reference Design .......................................................................................................... 67
13. GROUNDING AND LAYOUT .............................................................................................. 68
14. PIN DESCRIPTIONS ....................................................................................................... 70
15. PARAMETER AND TERM DEFINITIONS ............................................................................ 77
16. REFERENCE DESIGN ..................................................................................................... 79
17. REFERENCES ...................................................................................................................... 80
18. PACKAGE DIMENSIONS ..................................................................................................... 81
LIST OF FIGURES
Figure 1. Power Up Timing............................................................................................................ 10
Figure 2. Codec Ready from Start-up or Fault Condition .............................................................. 10
Figure 3. Clocks ............................................................................................................................ 10
Figure 4. Data Setup and Hold...................................................................................................... 11
Figure 5. PR4 Powerdown and Warm Reset ................................................................................ 11
Figure 6. Test Mode ...................................................................................................................... 11
Figure 7. AC-link Connections....................................................................................................... 12
Figure 8. CS4205 Mixer Diagram.................................................................................................. 14
Figure 9. Digital Signal Path Overview.......................................................................................... 15
Figure 10. Analog Centric Mode.................................................................................................... 17
Figure 11. Digital Centric Mode..................................................................................................... 17
Figure 12. Host Processing Mode ................................................................................................. 17
Figure 13. Multi-Channel Mode ..................................................................................................... 17
Figure 14. AC-link Input and Output Framing................................................................................ 18
Figure 15. Serial Data Port: Six Channel Circuit ........................................................................... 54
Figure 16. Digital Docking Connection Diagram ........................................................................... 55
Figure 17. Serial Data Format 0 (I2S) ........................................................................................... 56
Figure 18. Serial Data Format 1 (Left Justified) ............................................................................ 56
Figure 19. Serial Data Format 2 (Right Justified, 20-bit data) ....................................................... 56
Figure 20. Serial Data Format 3 (Right Justified, 16-bit data) ....................................................... 56
Figure 21. ZV Port Format (I2S, 16-bit data)................................................................................. 57
Figure 22. S/PDIF Output.............................................................................................................. 58
Figure 23. PLL External Loop Filter............................................................................................... 62
Figure 24. External Crystal............................................................................................................ 63
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Figure 25. Line Input (Replicate for Video and AUX) .................................................................... 64
Figure 26. Differential 2 VRMS CD Input ...................................................................................... 64
Figure 27. Differential 1 VRMS CD Input ...................................................................................... 64
Figure 28. Microphone Input ......................................................................................................... 65
Figure 29. PC_BEEP Input ........................................................................................................... 65
Figure 30. Modem Connection...................................................................................................... 65
Figure 31. Stereo Output............................................................................................................... 66
Figure 32. +5V Analog Voltage Regulator .................................................................................... 66
Figure 33. Conceptual Layout for the CS4205 when in XTAL or OSC Clocking Modes............... 69
Figure 34. Pin Locations for the CS4205 ...................................................................................... 70
Figure 35. CS4205 Reference Design .......................................................................................... 79
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