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CS4222
20-Bit Stereo Audio Codec with Volume Control
Features
l 99 dB 20-bit A/D Converters
l 99 dB 20-bit D/A Converters
l 110 dB DAC Signal-to-Noise Ratio (EIAJ)
l Analog Volume Control
- 0.5 dB Step Resolution
- 113.5 dB Attenuation
l Soft Mute Capability
l Differential Inputs/Outputs
l On-chip Anti-aliasing and Output Smoothing
Filters
l De-emphasis for 32, 44.1 and 48 kHz
l Stand-Alone or Control Port Mode
l Single +5 V power supply
Description
The CS4222 is a highly integrated, high performance,
20-bit, audio codec providing stereo analog-to-digital
and stereo digital-to-analog converters using delta-sig-
ma conversion techniques. The device operates from a
single +5 V power supply, and features low power con-
sumption. Selectable de-emphasis filter for 32, 44.1, and
48 kHz sample rates is also included.
The CS4222 also includes an analog volume control ca-
pable of 113.5 dB attenuation in 0.5 dB resolution. The
analog volume control architecture preserves dynamic
range during attenuation. Volume control changes are
implemented using a "soft" ramping or zero crossing
technique.
Applications include reverb processors, musical instru-
ments, DAT, and multitrack recorders.
The CS4222 is packaged in a 28-pin plastic SSOP.
ORDERING INFORMATION
CS4222-KS -10° to +70° C 28-pin SSOP
CDB4222
Evaluation Board
I
SCL/CCLK SDA/CDIN AD0/CS SMUTE MCLK VD VA
RST
DEM1
DEM0
LRCK
SCLK
SDIN
SDOUT
Control Port
Left Volume
DAC Control
Right Volume
DAC Control
Left
ADC
Right
ADC
AOUTL+
AOUTL-
AOUTR+
AOUTR-
AINL-
AINL+
AINR-
AINR+
DGND
AGND
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
JAN ‘97
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CS4222
ANALOG CHARACTERISTICS ( TA = 25°C; VA, VD = +5V; Full Scale Input Sine wave,
997 Hz; Fs = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in "Recom-
mended Connection Diagram"; SPI mode, Format 0, unless otherwise specified.)
Parameter
Symbol Min Typ Max Units
Analog Input Characteristics
ADC Resolution
- - 20 Bits
Total Harmonic Distortion
THD
0.003 - %
Dynamic Range
(A-weighted):
(unweighted):
TBD 99
TBD 96
- dB
- dB
Total Harmonic Distortion + Noise -1 dB
(Note 1) THD+N
-
-90
TBD
dB
Interchannel Isolation
(1 kHz)
- 90 - dB
Interchannel Gain Mismatch
- 0.1 - dB
Offset Error
(with High Pass Filter)
(HPF defeated with CAL)
- - 0 LSB
- TBD - LSB
Full Scale Input Voltage (Differential)
1.9 2.0 2.1 Vrms
Gain Drift
- 100 - ppm/°C
Input Resistance
10 -
- k
Input Capacitance
- - 15 pF
Common Mode Input Voltage
- 2.3 - V
A/D Decimation Filter Characteristics
Passband
(Note 2)
0 - 21.8 kHz
Passband Ripple
- - ±0.01 dB
Stopband
(Note 2)
30 - 6114 kHz
Stopband Attenuation
(Note 3)
80 -
- dB
Group Delay (Fs = Output Sample Rate)
Group Delay Variation vs. Frequency
High Pass Filter Characteristics
(Note 4) tgd
- 15/Fs -
s
tgd
-
-
0 µs
Frequency Response:
-3 dB
-0.1 dB
(Note 2)
- 3.7 - Hz
- 20 - Hz
Phase Deviation
@ 20 Hz
(Note 2)
- 10 - Degree
Passband Ripple
- - 0 dB
Notes:
1. Referenced to typical full-scale differential input voltage (2 Vrms)
2. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz,
the 0.01 dB passband edge is 0.4535xFs and the stopband edge is 0.625xFs.
3. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is
no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.8 kHz
where n = 0,1,2,3...).
4. Group delay for Fs = 48 kHz, tgd = 15/48 kHz = 312µs
* Parameter definitions are given at the end of this data sheet.
Specifications are subject to change without notice.
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CS4222
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol Min
Typ Max Units
Analog Output Characteristics - Minimum Attenuation, 10 k, 100 pF load; unless otherwise specified.
DAC Resolution
- - 20 Bits
Signal-to-Noise, Idle-Channel Noise (DAC muted, A-weighted)
TBD
110
-
dB
Dynamic Range
(DAC not muted, A-weighted)
(DAC not muted, unweighted)
TBD 99 - dB
TBD 96 - dB
Total Harmonic Distortion
THD
-
0.003
-
%
Total Harmonic Distortion + Noise
THD+N
-
-88 TBD dB
Interchannel Isolation
(1kHz)
- 90 - dB
Interchannel Gain Mismatch
- 0.1 - dB
Attenuation Step Size
(All Outputs)
0.35 0.5 0.65 dB
Programmable Output Attenuation Span
110 113.5
-
dB
Differential Offset Voltage
- ±10 - mV
Common Mode Output Voltage
- 2.3 - V
Full Scale Output Voltage
1.9 2.0 2.1 Vrms
Gain Drift
- 100 - ppm/°C
Out-of-Band Energy
(Fs/2 to 2Fs)
- -60 - dBFS
Analog Output Load
Resistance:
Capacitance:
10 - - k
- - 100 pF
Combined Digital and Analog Filter Characteristics
Frequency Response
10 Hz to 20 kHz
- ±0.1 - dB
Deviation from Linear Phase
- ±0.5 - Degrees
Passband: to 0.01 dB corner
(Notes 5,6)
0 - 21.8 kHz
Passband Ripple
(Note 6)
- - ±0.01 dB
Stopband
(Notes 5,6)
26.2 -
- kHz
Stopband Attenuation
(Notes 7)
70 - - dB
Group Delay (Fs = Input Word Rate)
tgd - 16 / Fs - s
Power Supply
Power Supply Current
VA
VD
Total Power Down
- 30 TBD mA
- 20 TBD mA
- 0.2 - mA
Power Supply Rejection Ratio
(1 kHz, 10 mVrms)
- 50 - dB
Notes: 5. The passband and stopband edges scale with frequency. For input word rates, Fs, other than
48 kHz, the 0.01 dB passband edge is 0.4535xFs and the stopband edge is 0.5465xFs.
6. Digital filter characteristics.
7. Measurement bandwidth is 10Hz to 3Fs.
Specifications are subject to change without notice
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CS4222
SWITCHING CHARACTERISTICS (TA = 25°C; VA, VD = +5V ±5%, outputs loaded with 30pF)
Parameter
Symbol Min
Typ Max Units
Audio ADC’s & DAC’s Sample Rate
Fs 4
- 50 kHz
MCLK Frequency
(MCLK = 256, 384, or 512 Fs)
1.024
-
26 MHz
MCLK Pulse Width High
MCLK = 512 Fs
MCLK = 384 Fs
MCLK = 256 Fs
10 - - ns
21 - - ns
31 - - ns
MCLK Pulse Width Low
MCLK = 512 Fs
MCLK = 384 Fs
MCLK = 256 Fs
10 - - ns
21 - - ns
31 - - ns
MCLK Jitter Tolerance
- 500 - ps RMS
RST Low Time
(Note 8)
10 - - ms
SCLK Falling edge to SDOUT output valid (DSCK=0)
tdpd -
-
1
(384)Fs
+
20
ns
LRCK edge to MSB valid
tlrpd -
- 25 ns
SDIN Setup Time Before SCLK Rising Edge
(DSCK=0) tds
-
- 25 ns
SDIN Hold Time After SCLK Rising Edge
SCLK Period
(DSCK=0)
tdh
tsckw
-
1
(128) Fs
-
-
25 ns
- ns
SCLK High Time
tsckh
40
-
- ns
SCLK Low Time
tsckl 40 - - ns
SCLK Rising to LRCK Edge
(DSCK=0) tlrckd
20
-
- ns
LRCK Edge to SCLK Rising
(DSCK=0) tlrcks
40
-
- ns
Notes: 8. After powering up the CS4222, PDN should be held low for 10 ms to allow the power supply
to settle.
LRCK
SCLK*
t lrckd
t lrcks
t sckh
tsckl
t sckw
SDIN
SDOUT
tlrpd tds
tdh
MSB
tdpd
MSB-1
*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.
Serial Audio Port Data I/O timing
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SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25°C VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30pF)
Parameter
Symbol
Min
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency
fsck -
RST rising edge to CS falling
tsrs 500
CCLK edge to CS falling
(Note 9)
tspi
500
CS High Time Between Transmissions
tcsh 1.0
CS Falling to CCLK Edge
tcss 20
CCLK Low Time
tscl 66
CCLK High Time
tsch 66
CDIN to CCLK Rising Setup Time
tdsu 40
CCLK Rising to DATA Hold Time
(Note 10)
tdh
15
Rise Time of CCLK and CDIN
(Note 11)
tr2
-
Fall Time of CCLK and CDIN
(Note 11)
tf2
-
Notes: 9. tspi only needed before first falling edge of CS after RST rising edge.
tspi = 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For FSCK < 1 MHz
CS4222
Max Units
6 MHz
- ns
- ns
- µs
- ns
- ns
- ns
- ns
- ns
100 ns
100 ns
RST
t srs
CS
CCLK
CDIN
t spi t css
t r2
t scl t sch
t f2
t dsu t dh
t csh
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