AD9993.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 AD9993 데이타시트 다운로드

No Preview Available !

Data Sheet
Integrated Mixed-Signal Front End (MxFE)
AD9993
FEATURES
Quad 14-bit 250 MSPS ADC
SFDR = 83 dBc at 87 MHz input
Dual 14-bit 500 MSPS DAC
SFDR = 75 dBc at 20 MHz output
On-chip PLL clock synthesizer
Low power
1536 mW, 1 GHz master clock, on-chip synthesizer
500 MHz double data rate (DDR)
LVDS interfaces for DACs and ADCs
Small 12 mm × 12 mm lead-free BGA package
APPLICATIONS
Point to point microwave backhaul radios
Wireless repeaters
GENERAL DESCRIPTION
The AD9993 is a mixed-signal front-end (MxFE®) device that
integrates four 14-bit ADCs and two 14-bit DACs. Figure 1
shows the block diagram of the MxFE. The MxFE is
programmable using registers accessed via a serial peripheral
interface (SPI). ADC and DAC datapaths include FIFO buffers
to absorb phase differences between LVDS lane clocks and the
data converter sampling clocks.
The MxFE DACs are part of the Analog Devices, Inc., high
speed CMOS DAC core family. These DACs are designed to be
used in wide bandwidth communication system transmitter
(Tx) signal chains.
The MxFE ADCs are multistage pipelined CMOS ADC cores
designed for use in communications receivers.
FUNCTIONAL BLOCK DIAGRAM
2 14
ADC_A
2 14
ADC_B
14
4
DCO CLOCK
STROBE
LVDS
BUFFER
DOUT3A_x TO DOUT0A_x
DOUT3B_x TO DOUT0B_x
DOUT3C_x TO DOUT0C_x
DOUT3D_x TO DOUT0D_x
DCO_x
STROBE_x
2 14
ADC_C
DIGITAL
–ADC AND DAC
DATAPATHS
14
DIN6A_x TO DIN0A_x
2
ADC_D
14
–CONTROLS
–SPI REGISTERS
LVDS
BUFFER
DIN6B_x TO DIN0B_x
–FIFO BUFFERS
DCI CLOCK
DCI_x
2 14
DAC_A
2 14
DAC_B
4 SPI_SCLK, SPI_CS, SPI_SDI, SPI_SDO
RST
ALERT
PLL
31.25MHz
OR
62.5MHz
DIV
0
1
1GHz
CLOCK GENERATOR
Figure 1.
MxFE
AD9993
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

No Preview Available !

AD9993
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 3 
Specifications..................................................................................... 4 
DC Specifications ......................................................................... 4 
AC Specifications.......................................................................... 5 
Digital Specifications ................................................................... 5 
Absolute Maximum Ratings............................................................ 7 
Thermal Resistance ...................................................................... 7 
ESD Caution.................................................................................. 7 
Pin Configuration and Function Descriptions............................. 8 
Typical Performance Characteristics ........................................... 11 
Receiver ADC Performance...................................................... 11 
Transmitter DAC Performance................................................. 13 
Terminology .................................................................................... 15 
Theory of Operation ...................................................................... 16 
Product Description................................................................... 16 
SPI Port ........................................................................................ 16 
SPI Configuration Programming............................................. 17 
Register Update Transfer Method ............................................ 17 
ADC Register Update Indexing................................................ 17 
ADCs............................................................................................ 17 
ADC Architecture ...................................................................... 17 
ADC Section Programming...................................................... 17 
Analog Input Considerations.................................................... 17 
DACs ............................................................................................ 18 
DAC Transfer Function ............................................................. 18 
DAC Output Compliance Voltage Range and AC
Performance ................................................................................ 18 
DAC Voltage Reference ............................................................. 19 
DAC Gain Setting....................................................................... 19 
DAC Datapath Format Selection.............................................. 19 
DAC Test Tone Generator DDS................................................ 19 
Clocking....................................................................................... 20 
On-Chip PLL Clock Multiplier ................................................ 20 
Selecting Clocking Options....................................................... 21 
ADC Datapath and DAC Datapath FIFOs ............................. 21 
LVDS Interfaces .......................................................................... 21 
LVDS Interface Timing.............................................................. 22 
LVDS Lane Testing Using PRBS............................................... 23 
Power Mode Programming....................................................... 23 
Interrupt Request Operation .................................................... 23 
Temperature Sensor ................................................................... 23 
Start-Up Register Sequences ......................................................... 25 
Power-Up Routine When Using the On-Chip Clock
Synthesizer .................................................................................. 25 
Power-Up Routine When Using External Clock ................... 25 
Applications Information .............................................................. 27 
Direct Conversion Radio Application ..................................... 27 
Register Map ................................................................................... 28 
Register Descriptions ..................................................................... 30 
SPI Configuration Register ....................................................... 30 
Chip ID Register......................................................................... 30 
Chip Grade Register................................................................... 31 
Device Index Register ................................................................ 31 
Power Mode Control Register .................................................. 32 
Align ADC LVDS Clocks, ADC FIFO, DAC FIFO Register 32 
Strobe Lane Control Register.................................................... 33 
Output Mode Register ............................................................... 33 
LVDS Tx Control Register ........................................................ 34 
VREF Control Register ................................................................. 34 
PRBS Generator Control Register............................................ 35 
8-Bit Seed MSB of PRBS Generator for Lane 0 Register....... 35 
8-Bit Seed MSB of PRBS Generator for Lane 1 Register....... 36 
8-Bit Seed MSB of PRBS Generator for Lane 2 Register....... 36 
8-Bit Seed MSB of PRBS Generator for Lane 3 Register....... 36 
Synthesizer Status Register........................................................ 37 
Loop Filter Control Signals Register........................................ 37 
Loop Filter Control Signals Register........................................ 38 
Loop Filter Control Signals Register........................................ 38 
Integer Value of Synthesizer Divider Register ........................ 39 
Synthesizer Control Register .................................................... 39 
Clock Generator Control Register ........................................... 39 
CLKGEN Control Register ....................................................... 40 
DAC LVDS Rx Control Register .............................................. 40 
DAC LVDS Current Bias Control Register ............................. 41 
DAC Cores Control Register .................................................... 42 
DAC Datapath Format Control Register ................................ 42 
Rev. A | Page 2 of 56

No Preview Available !

Data Sheet
DAC IQ Calibration Control Register......................................43 
DAC IQ Calibration Status Register .........................................43 
DAC Rx FIFO Status 1 Register ................................................43 
PRBS Detector Control Register ...............................................44 
PRBS Detector Error Count 0 for DAC A Register ................44 
PRBS Detector Error Count 1 for DAC A Register ................44 
PRBS Detector Error Count 2 for DAC A Register ................45 
PRBS Detector Error Count 3 for DAC A Register ................45 
PRBS Detector Error Count 4 for DAC A Register ................45 
PRBS Detector Error Count 5 for DAC A Register ................46 
PRBS Detector Error Count 6 for DAC A Register ................46 
PRBS Detector Error Count 0 for DAC B Register ................46 
PRBS Detector Error Count 1 for DAC B Register ................47 
PRBS Detector Error Count 2 for DAC B Register ................47 
PRBS Detector Error Count 3 for DAC B Register ................47 
PRBS Detector Error Count 4 for DAC B Register ................48 
PRBS Detector Error Count 5 for DAC B Register ................48 
REVISION HISTORY
5/14—Rev. 0 to Rev. A
Changes to Ordering Guide...........................................................56
5/14—Revision 0: Initial Version
AD9993
PRBS Detector Error Count 6 for DAC B Register ................48 
Bits[7:0] of Temperature Sensor Data Readback Register.....49 
Bits[15:8] of Temperature Sensor Data Readback Register...49 
Temperature Sensor Control Signals Register ........................49 
Interrupt Pin Control Register ..................................................50 
DDS Control Register.................................................................50 
DDS Tuning Word for Tone 1 Register ....................................51 
DDS Tuning Word for Tone 1 Register ....................................51 
DDS Tuning Word for Tone 1 Register ....................................52 
DDS Tuning Word for Tone 1 Register ....................................52 
Interrupt Status Register ............................................................53 
Interrupt Enable Register...........................................................53 
Interrupt Source Status Register ...............................................54 
Global Device Update Register .................................................55 
Outline Dimensions........................................................................56 
Ordering Guide ...........................................................................56 
Rev. A | Page 3 of 56

No Preview Available !

AD9993
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, unless otherwise noted.
Table 1.
Parameter
Tx DAC RESOLUTION
Tx DAC OUTPUT CHARACTERISTICS
Offset Error
Gain Error
Full-Scale Output Current (IOUTFS)
Output Compliance Voltage Range
Output Compliance Voltage Range
Output Resistance
Tx DAC TEMPERATURE DRIFT
Gain
Reference Voltage (VREF_DAC)
REFERENCE (VREF_DAC)
Internal Reference Voltage
Rx ADC RESOLUTION
Rx ADC CHARACTERISTICS
Gain Error
Peak-to-Peak Differential Input Voltage
Range
Input Capacitance
Rx ADC FULL-SCALE VREF ADJUSTMENT
COMMON-MODE VOLTAGE REFERENCE
(A_CML, B_CML, C_CML, D_CML)
ADC Common-Mode Voltage Output
ANALOG SUPPLY VOLTAGES
AVDD33
AVDD
DIGITAL SUPPLY VOLTAGES
DVDD
POWER CONSUMPTION
Single Tone Input, Single Tone Output
AVDD33
AVDD
DVDD
Power-Down Mode
OPERATING RANGE
Test Conditions/Comments
CML_A, CML_B connected to AVSS, setting of
DAC_VCM_VREF_BIT[2:0] following reset
CML_A, CML_B connected to a bypass capacitor,
DAC_VCM_VREF_BIT[2:0] set to 010
Gain using on-chip VREF_DAC
On-chip VREF_DAC
Setting of VREF_FS_ADJ[4:0] at reset
ADC inputs are not self biased
Data Sheet
Min Typ Max Unit
14 Bits
±0.5 % FSR
±2.0 % FSR
20.0 mA
−0.5 +0.5 V
0.0 1.0 V
10 MΩ
±85
±215
ppm/°C
ppm/°C
0.95 1.0
14
1.05 V
Bits
±1.0 % FSR
1.75 V p-p
2.5 pF
1.383 1.75 2.087 V
0.84 0.9 0.96 V
3.14 3.3
1.71 1.8
3.47 V
1.89 V
1.62 1.8 1.98 V
1536
mW
55 mA
65 mA
210 mA
10.0 mA
−40 +25 +85 °C
Rev. A | Page 4 of 56

No Preview Available !

Data Sheet
AD9993
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, DAC sampling rate = 500 MSPS and ADC sampling rate = 250 MSPS, unless
otherwise specified.
Table 2.
Parameter
DAC OUTPUT
Spurious-Free Dynamic Range
(SFDR)
Two Tone Intermodulation
Distortion (IMD3)
Noise Spectral Density (NSD),
Single Tone
256-QAM Adjacent Channel
Power (ACP)
ADC INPUT
Signal to Noise Ratio (SNR)
fIN = 87 MHz
Spurious-Free Dynamic Range
(SFDR)
fIN = 10 MHz
fIN = 87 MHz
Two-Tone IMD3
Full Power Bandwidth
Test Conditions/Comments
fOUT = 20 MHz
fOUT = 80 MHz
fOUT = 80 MHz
fCENTER = 50 MHz, single carrier, 3.375 MHz offset frequency
Min Typ Max Unit
75
65
−160
76
dBc
dBc
dBm/Hz
dBc
Measured with −1.0 dBFS sine wave input
Measured with −1.0 dBFS sine wave input
fIN1 = 89 MHz, fIN2 = 92 MHz, AIN = −12 dBFS
Bandwidth of operation in which proper ADC performance can be
achieved
70
86
83
90
1000
dBc
dBc
dBc
dBc
MHz
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, unless otherwise noted.
Table 3.
Parameter
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
CMOS OUTPUT LOGIC LEVEL
Output VOUT Logic High
Output VOUT Logic Low
ADC AND DAC LVDS DATA INTERFACES
ADC LVDS Transmitter Outputs
DCO_P/DCO_N to Data Skew (tSKEW)
Output Voltage High, VOH, Single
Ended
Output Voltage Low, VOL, Single
Ended
Output Differential Voltage
Output Offset Voltage
DAC LVDS Receiver Inputs
Input Voltage Range, Single Ended
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input
Impedance
Test Conditions/Comments
Data to DDR DCO_P/DCO_N transition delay
Applies to output voltage, positive and negative, VOUTP
and VOUTN
Applies to VOUTP and VOUTN
Specifications apply to DAC data inputs and DCI_P/DCI_N
Applies to input voltage, positive and negative, VINP and
VINN
Min Typ
1.8
0.0
1.2
350
1375
1025
200
1200
825
−100
25
85
Max Unit
V
V
V
0.8 V
ps
mV
mV
mV
mV
1575 mV
+100 mV
mV
115 Ω
Rev. A | Page 5 of 56