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Data Sheet No. PD60249
IRS2110(-1,-2,S)PbF
IRS2113(-1,-2,S)PbF
Features
HIGH AND LOW SIDE DRIVER
Floating channel designed for bootstrap operation Product Summary
Fully operational to +500 V or +600 V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 V to 20 V
VOFFSET (IRS2110)
(IRS2113)
500 V max.
600 V max.
Undervoltage lockout for both channels
IO+/-
2 A/2 A
3.3 V logic compatible
Separate logic supply range from 3.3 V to 20 V
VOUT
10 V - 20 V
Logic and power ground ± 5V offset
ton/off (typ.)
130 ns & 120 ns
CMOS Schmitt-triggered inputs with pull-down
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs
Delay Matching (IRS2110) 10 ns max.
(IRS2113) 20 ns max.
Packages
RoHS compliant
Description
The IRS2110/IRS2113 are high voltage, high speed
power MOSFET and IGBT drivers with independent
high-side and low-side referenced output channels. Pro-
prietary HVIC and latch immune CMOS technologies
enable ruggedized monolithic construction. Logic in-
puts are compatible with standard CMOS or LSTTL out-
14-Lead PDIP
IRS2110 and IRS2113
16-Lead PDIP
(w/o leads 4 & 5)
IRS2110-2 and IRS2113-2
put, down to 3.3 V logic. The output drivers feature a
high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are
matched to simplify use in high frequency applications.
The floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high-side configuration
which operates up to 500 V or 600 V.
14-Lead PDIP
(w/o lead 4)
IRS2110-1 and IRS2113-1
16-Lead SOIC
IRS2110S and
IRS2113S
Typical Connection
up to 500 V or 600 V
VDD
HIN
SD
LIN
VSS
VCC
HO
VDD
VB
HIN VS
SD
LIN VCC
VSS COM
LO
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connec-
tions only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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TO
LOAD
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IRS2110(-1,-2,S)PbF/IRS2113(-1,-2,S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figs. 28 through 35.
Symbol
Definition
Min. Max. Units
VB High-side floating supply voltage
(IRS2110)
(IRS2113)
-0.3 520 (Note 1)
-0.3 620 (Note 1)
VS High-side floating supply offset voltage
VHO High-side floating output voltage
VCC Low-side fixed supply voltage
VLO Low- side output voltage
VDD Logic supply voltage
VB - 20
VS - 0.3
-0.3
-0.3
-0.3
VB + 0.3
VB + 0.3
20 (Note 1)
VCC + 0.3
VSS+20
(Note 1)
V
VSS
VIN
dVs/dt
PD
Logic supply offset voltage
Logic input voltage (HIN, LIN, & SD)
Allowable offset supply voltage transient (Fig. 2)
(14 lead DIP)
Package power dissipation @ TA +25 °C
(16 lead SOIC)
VCC - 20
VSS - 0.3
VCC + 0.3
VDD + 0.3
50
1.6
1.25
V/ns
W
RTHJA
Thermal resistance, junction to ambient
(14 lead DIP)
(16 lead SOIC)
75
°C/W
100
TJ Junction temperature
TS Storage temperature
— 150
-55 150 °C
TL Lead temperature (soldering, 10 seconds)
— 300
Note 1: All supplies are fully tested at 25 V, and an internal 20 V clamp exists for each supply.
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at a 15 V differential.
Typical ratings at other bias conditions are shown in Figs. 36 and 37.
Symbol
Definition
Min. Max. Units
VB High-side floating supply absolute voltage
(IRS2110)
VS High-side floating supply offset voltage
(IRS2113)
VS + 10
Note 2
Note 2
VS + 20
500
600
VHO High-side floating output voltage
VS VB
VCC Low-side fixed supply voltage
10 20 V
VLO Low- side output voltage
0 VCC
VDD Logic supply voltage
VSS + 3
VSS + 20
VSS Logic supply offset voltage
-5 (Note 3)
5
VIN Logic input voltage (HIN, LIN & SD)
VSS
VDD
TA Ambient temperature
-40 125 °C
Note 2: Logic operational for VS of -4 V to +500 V. Logic state held for VS of -4 V to -VBS. (Refer to the Design Tip DT97-3)
Note 3: When VDD < 5 V, the minimum VSS offset is limited to -VDD.
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IRS2110(-1,-2,S)PbF/IRS2113(-1,-2,S)PbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS, VDD) = 15 V, CL = 1000 pF, TA = 25 °C and VSS = COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Fig. 3.
Symbol
Definition
ton Turn-on propagation delay
toff Turn-off propagation delay
tsd Shutdown propagation delay
tr Turn-on rise time
tf Turn-off fall time
Delay matching, HS & LS (IRS2110)
MT turn-on/off
(IRS2113)
Min. Typ. Max. Units Test Conditions
— 130 160
VS = 0 V
— 120 150
VS = 500 V/600 V
— 130 160
ns
— 25 35
— 17 25
— — 10
— — 20
Static Electrical Characteristics
VBIAS (VCC, VBS, VDD) = 15 V, TA = 25 °C and VSS = COM unless otherwise specified. The VIN, VTH, and IIN parameters
are referenced to VSS and are applicable to all three logic input leads: HIN, LIN, and SD. The VO and IO parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
VIH
VIL
VOH
VOL
ILK
IQBS
IQCC
IQDD
IIN+
IIN-
VBSUV+
VBSUV-
VCCUV+
VCCUV-
Definition
Logic “1” input voltage
Logic “0” input voltage
High level output voltage, VBIAS - VO
Low level output voltage, VO
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
Quiescent VDD supply current
Logic “1” input bias current
Logic “0” input bias current
VBS supply undervoltage positive going
threshold
VBS supply undervoltage negative going
threshold
VCC supply undervoltage positive going
threshold
VCC supply undervoltage negative going
threshold
IO+ Output high short circuit pulsed current
IO- Output low short circuit pulsed current
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Min. Typ. Max. Units Test Conditions
9.5 — —
— — 6.0
— — 1.4 V
IO = 0 A
— — 0.15
IO = 20 mA
— — 50
VB=VS = 500 V/600 V
— 125 230
— 180 340 µA VIN = 0 V or VDD
— 15 30
— 20 40
— — 5.0
VIN = VDD
VIN = 0 V
7.5 8.6 9.7
7.0 8.2 9.4
7.4 8.5 9.6
V
7.0 8.2 9.4
2.0 2.5 —
2.0 2.5 —
VO = 0 V, VIN = VDD
PW 10 µs
A VO = 15 V, VIN = 0V
PW 10 µs
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IRS2110(-1,-2,S)PbF/IRS2113(-1,-2,S)PbF
Functional Block Diagram
VDD
HIN
SD
RQ
S
VDD /VCC
LEVEL
SHIFT
PULSE
GEN
HV
LEVEL
SHIFT
UV
DETECT
PULSE
FILTER
RQ
R
S
VDD /VCC
LIN LEVEL
S
RQ
SHIFT
UV
DETECT
DELAY
VSS
VB
HO
VS
VCC
LO
COM
Lead Definitions
Symbol Description
VDD
HIN
SD
LIN
VSS
VB
HO
VS
VCC
LO
COM
Logic supply
Logic input for high-side gate driver output (HO), in phase
Logic input for shutdown
Logic input for low-side gate driver output (LO), in phase
Logic ground
High-side floating supply
High-side gate drive output
High-side floating supply return
Low-side supply
Low-side gate drive output
Low-side return
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IRS2110(-1,-2,S)PbF/IRS2113(-1,-2,S)PbF
Lead Assignments
14 Lead PDIP
IRS2110/IRS2113
16 Lead SOIC (Wide Body)
IRS2110S/IRS2113S
14 Lead PDIP w/o lead 4
IRS2110-1/IRS2113-1
Part Number
16 Lead PDIP w/o leads 4 & 5
IRS2110-2/IRS2113-2
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