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Intel® Advanced Boot Block Flash
Memory (B3)
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
Product Features
Flexible SmartVoltage Technology
— 2.7 V – 3.6 V read/program/erase
— 12 V VPP fast production programming
1.65 V – .5 V or 2.7 V – 3.6 V I/O option
— Reduces overall system power
High Performance
— 2.7 V – 3.6 V: 70 ns max access time
Optimized Block Sizes
— Eight 8-KB blocks for data, top or
bottom locations
— Up to 127 x 64-KB blocks for code
Block Locking
— VCC-level control through Write Protect
WP#
Low Power Consumption
— 9 mA typical read current
Absolute Hardware-Protection
— VPP = GND option
— VCC lockout voltage
Extended Temperature Operation
— –40 °C to +85 °C
Automated Program and Block Erase
— Status registers
Intel® Flash Data Integrator Software
—Flash Memory Manager
—System Interrupt Manager
—Supports parameter storage, streaming
data (for example, voice)
Extended Cycling Capability
—Minimum 100,000 block erase cycles
Automatic Power Savings Feature
—Typical ICCS after bus inactivity
Standard Surface Mount Packaging
—48-Ball CSP packages
—40-Lead and 48-Lead TSOP packages
Density and Footprint Upgradeable for
common package
—8-, 16-, 32-, and 64-Mbit densities
ETOX™ VIII (0.13 µm) Flash
Technology
—16-Mbit and 32-Mbit densities
ETOX™ VII (0.18 µm) Flash Technology
—16-, 32-, and 64-Mbit densities
ETOX ™ VI (0.25µm) Flash Technology
—8-, 16-, and 32-Mbit densities
Bo not use the x8 option for new designs
The Intel® Advanced Boot Block Flash Memory (B3) device, manufactured on the Intel 0.13 µm
and 0.18 µm technologies, is a feature-rich solution at a low system cost. The B3 device in x16 is
available in 48-lead TSOP and 48-ball CSP packages. The x8 option of this product family is
available only in 40-lead TSOP and 48-ball µBGA* packages. For additional information about
this product family, see the Intel website: http://www.intel.com/design/flash.
Notice: This specification is subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
Order Number: 290580, Revision: 020
18 Aug 2005

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel® Advanced Boot Block Flash Memory (B3) may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800
548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, the Intel logo, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation.
18 Aug 2005
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Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet

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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Contents
1.0 Introduction ............................................................................................................................... 7
1.1 Nomenclature ....................................................................................................................... 7
1.2 Conventions .......................................................................................................................... 8
2.0 Functional Overview .............................................................................................................. 8
3.0 Functional Overview .............................................................................................................. 9
3.1 Architecture Diagram .......................................................................................................... 10
3.2 Memory Maps and Block Organization ............................................................................... 11
3.2.1 Parameter Blocks .................................................................................................. 11
3.2.2 Main Blocks ........................................................................................................... 11
3.2.3 4-Mbit, 8-Mbit, 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Maps ............. 11
3.2.4 4-Mbit, 8-Mbit, and 16-Mbit Byte-Wide Memory Maps........................................... 20
4.0 Package Information ............................................................................................................ 24
4.1 mBGA* and Very Thin Profile Fine Pitch Ball Grid Array (VF BGA) Package .................... 24
4.2 TSOP Package ................................................................................................................... 25
4.3 Easy BGA Package ............................................................................................................ 26
5.0 Pinout and Signal Descriptions....................................................................................... 27
5.1 Signal Pinouts ..................................................................................................................... 27
5.1.1 40-Lead and 48-Lead TSOP Packages ................................................................. 27
5.2 Signal Descriptions ............................................................................................................. 30
6.0 Maximum Ratings and Operating Conditions ...........................................................32
6.1 Absolute Maximum Ratings ................................................................................................ 32
6.2 Operating Conditions .......................................................................................................... 33
7.0 Electrical Specifications ..................................................................................................... 34
7.1 DC Current Characteristics .................................................................................................34
7.2 DC Voltage Characteristics.................................................................................................36
8.0 AC Characteristics ................................................................................................................ 37
8.1 AC Read Characteristics .................................................................................................... 37
8.2 AC Write Characteristics..................................................................................................... 41
8.3 Erase and Program Timing .................................................................................................45
8.4 AC I/O Test Conditions ....................................................................................................... 46
8.5 Device Capacitance ............................................................................................................ 46
9.0 Power and Reset Specifications .....................................................................................47
9.1 Power-Up/Down Characteristics ......................................................................................... 47
9.1.1 RP# Connected to System Reset .......................................................................... 47
9.1.2 VCC, VPP, and RP# Transitions..............................................................................47
9.2 Reset Specifications ........................................................................................................... 48
9.3 Power Supply Decoupling................................................................................................... 49
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
3

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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.4 Power Consumption ........................................................................................................... 49
9.4.1 Active Power.......................................................................................................... 49
9.4.2 Automatic Power Savings (APS) ........................................................................... 49
9.4.3 Standby Power ...................................................................................................... 49
9.4.4 Deep Power-Down Mode....................................................................................... 50
10.0 Operations Overview ........................................................................................................... 50
10.1 Bus Operations ................................................................................................................... 51
10.1.1 Read ...................................................................................................................... 51
10.1.2 Output Disable ....................................................................................................... 52
10.1.3 Standby.................................................................................................................. 52
10.1.4 Deep Power-Down / Reset .................................................................................... 52
10.1.5 Write ...................................................................................................................... 53
11.0 Operating Modes ................................................................................................................... 53
11.1 Read Array.......................................................................................................................... 54
11.2 Read Identifier .................................................................................................................... 56
11.3 Read Status Register.......................................................................................................... 56
11.3.1 Clearing the Status Register.................................................................................. 57
11.4 Program Mode .................................................................................................................... 57
11.4.1 Suspending and Resuming Programming ............................................................. 58
11.5 Erase Mode ........................................................................................................................ 58
11.5.1 Suspending and Resuming Erase ......................................................................... 59
12.0 Block Locking ......................................................................................................................... 62
12.1 WP# = VIL for Block Locking............................................................................................... 62
12.2 WP# = VIH for Block Unlocking........................................................................................... 62
13.0 VPP Program and Erase Voltages ................................................................................... 63
13.1 VPP = VIL for Complete Protection...................................................................................... 63
14.0 Additional Information ........................................................................................................ 63
Appendix A Write State Machine Current/Next States ................................................. 64
Appendix B Program and Erase Flowcharts .................................................................... 66
Appendix C Ordering Information......................................................................................... 70
18 Aug 2005
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Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet

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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Revision
Number
-001
-002
-003
-004
-005
-006
Description
Original version
Section 3.4, VPP Program and Erase Voltages, added
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
IPPR maximum specification change from ±25 µA to ±50 µA
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V VPP read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A1–A20 = 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW and ICCW into one specification (Section 4.4)
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 µs typical and 20 µs maximum
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA package diagrams corrected (Figures 3 and 4)
IPPD test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
VIH and VILSpecification change (Section 4.4)
ICCS test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
5