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IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
16Mb Async/Page PSRAM
NOVEMBER 2015
Overview
The IS66/67WVE1M16EALL/BLL/CLL and IS66/67WVE1M16TALL/BLL/CLL are integrated memory device
containing 16Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 1M
words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where
data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby
current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate
power supply from the device core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
Page mode read access
Interpage Read access : 60ns, 70ns
Intrapage Read access : 25ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 23mA
Standby < 150 µA (max.)
Deep power-down (DPD)
ALL/CLL: < 3µA (Typ)
BLL: < 10µA (Typ)
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
Industrial: -40°C~85°C
Automotive A1: -40°C~85°C
Packages:
48-ball TFBGA, 48-pin TSOP-I
Notes :
1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at sram@issi.com for
additional information.
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. C | Oct. 2015
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IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
General Description
PSRAM products are high-speed, CMOS pseudo-static random access memory developed
for low-power, portable applications. The 16Mb DRAM core device is organized
as 1 Meg x 16 bits. These devices include the industry-standard, asynchronous memory
interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings.
For seamless operation on an asynchronous memory bus, PSRAM products incorporated a
transparent self-refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device read/write
performance.
A user-accessible configuration registers (CR) defines how the PSRAM device performs on-
chip refresh and whether page mode read accesses are permitted. This register is
automatically loaded with a default setting during power-up and can be updated at any
time during normal operation.
Special attention has been focused on current consumption during self-refresh. This
product includes two system-accessible mechanisms to minimize refresh current.
Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array
refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts refresh operation altogether and is
used when no vital information is stored in the device. The system-configurable refresh
mechanisms are accessed through the CR.
A0~A19
Address
Decode Logic
Configuration Register
(CR)
1M X 16
DRAM
Memory Array
Input
/Output
Mux
And
Buffers
CE#
WE#
OE#
LB#
UB#
ZZ#
Control
Logic
Rev. C | Oct. 2015
[ Functional Block Diagram]
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DQ0~DQ15
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IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
48Ball TFBGA Ball Assignment
1 23 456
A
LB# OE#
A0
A1 A2 ZZ#
B
DQ8 UB#
A3
A4 CE# DQ0
C
DQ9 DQ10
A5
A6 DQ1 DQ2
D
VSSQ DQ11 A17
A7 DQ3 VDD
E
VDDQ DQ12
NC
A16 DQ4 VSS
F
DQ14 DQ13 A14
A15 DQ5 DQ6
G
DQ15 A19
A12
A13 WE# DQ7
H
A18 A8
A9
A10 A11
NC
[Top View]
(Ball Down)
Rev. C | Oct. 2015
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48-pin TSOP-I (Top View)
IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
Notes :
1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at
sram@issi.com for additional information.
Rev. C | Oct. 2015
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IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
Signal Descriptions
All signals for the device are listed below in Table 1.
Table 1. Signal Descriptions
Symbol
VSS
VSSQ
DQ0~DQ15
A0~A19
LB#
UB#
CE#
OE#
WE#
ZZ#
Type
Power Supply
Power Supply
Input / Output
Input
Input
Input
Input
Input
Input
Input
Description
All VSS supply pins must be connected to Ground
All VSSQ supply pins must be connected to Ground
Data Inputs/Outputs (DQ0~DQ15)
Address Input (A0~A19)
Lower Byte select
Upper Byte select
Chip Enable/Select
Output Enable
Write Enable
Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device
can enter one of two low-power modes ( DPD or PAR).
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
Rev. C | Oct. 2015
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