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bq24741, bq24742
www.ti.com
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
Li-Ion or Li-Polymer Battery Charger with Low Iq and Accurate Trickle Charge
Check for Samples :bq24741 bq24742
FEATURES
1
• NMOS-NMOS Synchronous Buck Converter
• Resistor-Programmable Switching Frequency
between 300 kHz and 800 kHz
• 9 V-24 V Input Voltage Operation Range
• Support Two to Four Cells
• Analog Inputs with Ratiometric Programming
via Resistors or DAC/GPIO
– Charge Voltage (4-4.512 V/cell)
– Charge Current (up to 10 A)
– Adapter Current Limit for DPM
• High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
– ±2% Input Current Sense Amp Accuracy
• 150 mA Trickle-charge Current with ±33%
Accuracy Down to Zero Battery Voltage
• Safety Protection
– Input Overvoltage Protection
– Battery Overvoltage Protection
– Charger Overcurrent Protection
– Thermal Shutdown Protection
– FET/Inductor/Battery Short Protection
• Status and Monitoring Outputs
– Adapter Present Indicator
– Programmable Input Power Detect with
Adjustable Threshold
– Dynamic Power Management (DPM) with
Status Indicator
– Current Drawn from Input Source
• Charge Enable Pin
• Internal Soft-Start and Loop Compensation
• 25 ns Minimum Driver Dead-Time and 99.5%
Maximum Effective Duty Cycle
• 28-pin, 5x5-mm2 QFN package
• Energy Star Low Quiescent Current Iq
– < 10 μA Off-State Battery Discharge Current
– < 1.5 mA Off-State Input Quiescent Current
APPLICATIONS
• Notebook and Ultra-Mobile PC
• Portable Data Capture Terminals
• Portable Printers
• Medical Diagnostics Equipment
• Battery Bay Chargers
• Battery Back-up Systems
DESCRIPTION
The bq24741/2 is a high-efficiency, synchronous
battery charger with integrated compensation,
offering low component count for space-constrained
Li-ion or Li-polymer battery charging applications.
Ratiometric charge current and voltage programming
allows high regulation accuracies, and can be either
hardwired with resistors or programmed by the
system power-management microcontroller using a
DAC or GPIOs.
The bq24741/2 charges two, three, or four series Li+
cells, supporting up to 10 A of charge current, and is
available in a 28-pin, 5x5-mm2 thin QFN package.
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CE 1
ACN 2
ACP 3
LPMOD 4
ACDET 5
ACSET 6
LPREF 7
28 27 26 25 24 23 22
bq24741/2
QFN-28
TOP VIEW
21 DPMDET
20 CELLS
19 CSP
18 CSN
17 BAT
16 ISET
15 IADAPT
8 9 10 11 12 13 14
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated

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bq24741, bq24742
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The bq24741/2 features resistor-programmable PWM switching frequency and accurate 150mA trickle charge
(with 20 msensing resistor), which can be enabled via the TRICKLE pin. The bq24741/2 also features Dynamic
Power Management (DPM) and input power limiting. These features reduce battery charge current when the
input power limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger
simultaneously. A high-accuracy current sense amplifier enables accurate measurement of input current from the
AC adapter, allowing monitoring the overall system power. If the adapter current is above the programmed
low-power threshold, a signal is sent to host so that the system optimizes its power performance according to
what is available from the adapter.
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ADAPTER +
ADAPTER -
R11
C1
2.2 µF
PP
Q1 (ACFET) Q2 (ACFET)
SI4435
SI4435
Controlled by
HOST
C2
R1
432 kΩ
0.1 µF
1%
RAC
0.010 Ω
C3
0.1 µF
EXTPWR
R2
66.5 kΩ
1%
R3 VREF
10 kΩ
R4
10 kΩ
R5
10 kΩ
GPIO
C4
1 µF
HOST
ISET_PWM
(D = 0.72, Vpeak = VDAC)
ADC
R15
10 kΩ
120 kΩ
R14
C13
100 nF
C5
100 pF
VREF
R12
102 kΩ
1%
R13
64.9 kΩ
1%
R16
10 Ω
D2
BAT54
C6 C7
10 µF 10 µF
ACN
ACP
PVCC
ACDET
AGND
HIDRV
EXTPWR
VREF
SW
BTST
bq24741/2 REGN
TRICKLE
DPMDET
LPMOD
CELLS
CE
VDAC
ISET
LODRV
PGND
CSP
CSN
BAT
IADAPT
LPREF
VADJ
ACSET
PowerPad FSET
C8
0.1 µF
C9
D1 BAT54 0.1 µF
C10
1 µF
Q3(BATFET)
SI4435
Controlled by
HOST
Q4_A
FDS8978
L1
P
RSR
0.020 Ω
10 µH
C11
10 µF
C13
0.1 µF
Q4_B
FDS8978
C14
0.1 µF
C12
10 µF
VREF
R9
60.4 kΩ
1%
R6
97.6 kΩ
R10
40.2 kΩ
1%
VREF
R7
73.2 kΩ
1%
R8
26.7 kΩ
1%
C15
0.1 µF
SYSTEM
PACK+
PACK-
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FS = 400 kHz, 90 W Adapter, VADAPTER = 19 V, VBAT = 3-cell Li-Ion (4.2V/cell), Icharge = 3.6 A, Iadapter_limit = 4.0 A
Figure 1. Typical System Schematic, Voltage, and Current Programmed by Resistor
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Text for space
ADAPTER +
ADAPTER -
R11
C1
2.2 µF
PP
Q1 (ACFET) Q2 (ACFET)
SI4435
SI4435
Controlled by
HOST
C2
R1
432 kΩ
0.1 µF
1%
RAC
0.010 Ω
C3
0.1 µF
EXTPWR
R2
66.5 kΩ
1%
VREF
R3
10 kΩ
R4
10 kΩ
R5
10 kΩ
GPIO
C4
1 µF
HOST
ISET _PWM
(D = 0.72, Vpeak = VDAC)
DAC
ADC
R15
10 kΩ
120 kΩ
R14
C13
100 nF
C5
100 pF
bq24741, bq24742
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
R16
10 Ω
D2
BAT54
C6 C7
10 µF 10 µF
SYSTEM
ACN
ACP
PVCC
ACDET bq24741/2
AGND
HIDRV
EXTPWR
VREF
SW
BTST
REGN
TRICKLE
DPMDET
LPMOD
CELLS
CE
VDAC
ISET
LODRV
PGND
CSP
CSN
BAT
ACSET
VADJ
IADAPT PowerPad
LPREF
FSET
C8
0.1 µF
C9
D1 BAT54 0.1 µF
C10
1 µF
Q3 (BATFET)
SI4435
Controlled by
HOST
Q4_A
FDS8978
L1
P
RSR
0.020 Ω
4.7 µH
C11
10 µF
C13
0.1 µF
Q4_B
FDS8978
C14
0.1 µF
R6
56.2 kΩ
VREF
R7
73.2 kΩ
1%
R8
26.7 kΩ
1%
C15
0.1 µF
C12
10 µF
PACK+
PACK-
Text for space
(1) Pull-up rail could be either VREF or other system rail.
(2) SRSET/ACSET could come from either DAC or resistor dividers.
FS = 650 kHz, 90 W Adapter, VADAPTER = 19 V, VBAT = 3-cell Li-Ion (4.2V/cell), Icharge = 3.6 A, Iadapter_limit = 4.0 A
Figure 2. Typical System Schematic, Voltage and Current Programmed by DAC
Part number
bq24741
bq24742
ORDERING INFORMATION
Package
Ordering Number
(Tape and Reel)
28-PIN 5 x 5 mm2 QFN
bq24741RHDR
bq24741RHDT
28-PIN 5 x 5 mm2 QFN
bq24742RHDR
bq24742RHDT
Quantity
3000
250
3000
250
PACKAGE THERMAL DATA
PACKAGE
QFN – RHD(1) (2)
θJA
39°C/W
TA = 25°C POWER RATING
2.36 W
DERATING FACTOR ABOVE TA = 25°C
0.028 W/°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24741 bq24742
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SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
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PIN
NAME
NO.
CE 1
ACN
2
ACP
3
LPMOD
4
ACDET
5
ACSET
6
LPREF
7
TRICKLE 8
AGND
9
VREF
10
VDAC
11
VADJ
12
EXTPWR 13
FSET
IADAPT
14
15
ISET
16
BAT 17
CSN
CSP
CELLS
18
19
20
Table 1. Pin Functions – 28-Pin QFN
DESCRIPTION
Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1 Mpull-down
resistor. A 10 Kexternal resistor is required to connect the CE pin to the external pull-up rail other than VREF.
Adapter current sense resistor, negative input. A 0.1 μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. An optional 0.1 μF ceramic capacitor is placed from ACN pin to AGND for common-mode
filtering.
Adapter current sense resistor, positive input. A 0.1 μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. A 0.1 μF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.
Low-power-mode-detect active-LOW open-drain logic output. Place a 10kohm pull-up resistor from LPMOD pin to the
pull-up voltage rail. The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The output is LOW
when IADAPT pin voltage is higher than LPREF pin voltage. Internal 6% hysteresis.
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter
input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET pin voltage is greater than 2.4 V. IADAPT
current sense amplifier is active when ACDET pin voltage is greater than 0.6V and PVCC > VUVLO. ACOV is input
over-voltage protection; it disables charge when ACDET > 3.1 V. ACOV does not latch, and normal operation resumes
when ACDET < 3.1 V.
Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC to
ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to the
VDAC pin.
Low power voltage set input. Connect a resistor divider from VREF to LPREF, and AGND to program the reference for
the LOPWR comparator. The LPREF pin voltage is compared to the IADAPT pin voltage and the logic output is given
on the LPMOD open-drain pin. Connect LPREF to ACSET through a resistor divider to track the adapter power.
Trickle current enable logic input. When CE is HIGH, a HIGH level on this pin enables accurate 150 mA trickle charge
with 20 msense resistor. A LOW level on this pin enables the ISET pin to program the charge current. It has an
internal 1Mpull-down resistor.
Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the
analog ground plane, and only connect to PGND through the PowerPad underneath the IC.
3.3 V regulated voltage output. Place a 1 μF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
could be used for ratio-metric programming of voltage and current regulation and for programming the LPREF
threshold. VREF is also the voltage source for the internal circuit.
Charge voltage set reference input. Connect the VREF or external DAC voltage source to VDAC pin. Battery voltage,
charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the voltage on VADJ, and
ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, ISET, and ACSET pins to AGND for
programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output to VADJ, ISET,
or ACSET.
Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage
regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the
output of an external DAC to VADJ pin and connect the DAC supply to VDAC pin.
Valid adapter active-low detect logic open-drain output. Pulled LO when Input voltage is above ACDET programmed
threshold OR input current is greater than 1.25 A with 10 msense resistor. Connect a 10 kpull-up resistor from
EXTPWR pin to pull-up supply rail.
PWM switching frequency (Fs) program pin. Program the switching frequency by placing a resistor to AGND on this pin.
Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
100pF (max) or less ceramic decoupling capacitor from IADAPT to AGND.
Charge current set input. The voltage ratio of ISET voltage versus VDAC voltage programs the charge current
regulation set-point. Program by connecting a resistor divider from VDAC to ISET, to AGND; or, by connecting the
output of an external DAC to ISET pin and connect the DAC supply to VDAC pin.
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT
pin to accurately sense the battery pack voltage. Place a 0.1 μF capacitor from BAT to AGND close to the IC to filter
high frequency noise.
Charge current sense resistor, negative input. A 0.1 μF ceramic capacitor is placed from CSN to CSP to provide
differential-mode filtering. An optional 0.1 μF ceramic capacitor is placed from CSN pin to AGND for common-mode
filtering.
Charge current sense resistor, positive input. A 0.1 μF ceramic capacitor is placed from CSN to CSP to provide
differential-mode filtering. A 0.1 μF ceramic capacitor is placed from CSP pin to AGND for common-mode filtering.
2, 3 or 4 cells selection logic input. Logic Lo programs 3–cell. Logic HI programs 4-cell. Floating programs 2–cell.
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bq24741, bq24742
SLUS875B – MARCH 2009 – REVISED OCTOBER 2009
Table 1. Pin Functions – 28-Pin QFN (continued)
PIN
NAME
NO.
DPMDET 21
PGND
LODRV
REGN
22
23
24
SW
HIDRV
BTST
25
26
27
PVCC
28
PowerPad
DESCRIPTION
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low (LO) indicates input
current is being limited by reducing the charge current. Connect 10-kohm pull-up resistor from DPMDET pin to VREF or
a different pull-up supply rail.
Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of
low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to AGND
through the PowerPad underneath the IC.
PWM low side driver output. Connect to the gate of the low–side power MOSFET with a short and wide trace.
PWM low side driver positive supply output. Connect a 1 μF ceramic capacitor from REGN to PGND pin, close to the
IC. Use for low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from
REGN to BTST. REGN is disabled when CE is LOW.
PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET
drain, high-side power MOSFET source, and output inductor). Connect the 0.1 μF bootstrap capacitor from SW to
BTST.
PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
PWM high side driver positive supply. Connect a 0.1 μF bootstrap ceramic capacitor from BTST to SW. Connect a
bootstrap Schottky diode from REGN to BTST. A optional 2.0- 5.1bootstrap resistor can be inserted between the
BTST pin and the common point of the bootstrap capacitor and bootstrap diode, thus dampening the SW node voltage
ring and spike.
IC power positive supply. Connect to the adapter input through a schottky diode. Place a 0.1 uF ceramic capacitor from
PVCC to PGND pin close to the IC.
Exposed pad beneath the IC. AGND and PGND star-connected only at the PowerPad plane. Always solder PowerPad
to the board, and have vias on the PowerPad plane connecting to AGND and PGND planes. It also serves as a thermal
pad to dissipate the heat.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1) (2)
Voltage range
Maximum difference voltage
Junction temperature range
Storage temperature range
PVCC, ACP, ACN, CSP, CSN, BAT
SW
REGN, LODRV, VADJ, ACSET, ISET, ACDET, FSET, IADAPT, LPMOD,
LPREF, CE, CELLS, EXTPWR, DPMDET, TRICKLE
VDAC, VREF
BTST, HIDRV with respect to AGND and PGND
AGND, PGND
ACP–ACN, CSP–CSN
VALUE
–0.3 to 30
–1 to 30
–0.3 to 7
–0.3 to 3.6
–0.3 to 36
–1 to 1
-0.5 to 0.5
–40 to 155
–55 to 155
UNIT
V
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
Copyright © 2009, Texas Instruments Incorporated
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