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April 1992
COP424C COP425C COP426C COP324C COP325C
COP326C and COP444C COP445C COP344C COP345C
Single-Chip 1k and 2k CMOS Microcontrollers
General Description
The COP424C COP425C COP426C COP444C and
COP445C fully static Single-Chip CMOS Microcontrollers
are members of the COPSTM family fabricated using dou-
ble-poly silicon gate microCMOS technology These Con-
troller Oriented Processors are complete microcomputers
containing all system timing internal logic ROM RAM and
I O necessary to implement dedicated control functions in a
variety of applications Features include single supply oper-
ation a variety of output configuration options with an in-
struction set internal architecture and I O scheme de-
signed to facilitate keyboard input display output and BCD
data manipulation The COP424C and COP444C are 28 pin
chips The COP425C and COP445C are 24-pin versions (4
inputs removed) and COP426C is 20-pin version with 15 I O
lines Standard test procedures and reliable high-density
techniques provide the medium to large volume customers
with a customized microcontroller at a low end-product cost
These microcontrollers are appropriate choices in many de-
manding control environments especially those with human
interface
The COP424C is an improved product which replaces the
COP420C
COPSTM MicrobusTM and MICROWIRETM are trademarks of National Semiconductor Corp
TRI-STATE is a registered trademark of National Semiconductor Corp
Features
Y Lowest power dissipation (50 mW typical)
Y Fully static (can turn off the clock)
Y Power saving IDLE state and HALT mode
Y 4 ms instruction time plus software selectable clocks
Y 2k x 8 ROM 128 x 4 RAM (COP444C COP445C)
Y 1k x 8 ROM 64 x 4 RAM (COP424C COP425C
COP426C)
Y 23 I O lines (COP444C and COP424C)
Y True vectored interrupt plus restart
Y Three-level subroutine stack
Y Single supply operation (2 4V to 5 5V)
Y Programmable read write 8-bit timer event counter
Y Internal binary counter register with MICROWIRETM
serial I O capability
Y General purpose and TRI-STATE outputs
Y LSTTL CMOS output compatible
Y MicrobusTM compatible
Y Software hardware compatible with COP400 family
Y Extended temperature range devices COP324C
COP325C COP326C and COP344C COP345C (b40 C
to a85 C)
Y Military devices (b55 C to a125 C) to be available
Block Diagram
C1995 National Semiconductor Corporation TL DD 5259
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FIGURE 1
Not available on COP426C COP326C
TL DD 5259 – 1
RRD-B30M105 Printed in U S A

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COP424C COP425C COP426C and COP444C COP445C
Absolute Maximum Ratings
Supply Voltage (VCC)
Voltage at any Pin
Total Allowable Source Current
Total Allowable Sink Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(soldering 10 seconds)
6V
b0 3V to VCC a 0 3V
25 mA
25 mA
0 C to a70 C
b65 C to a150 C
300 C
Note Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics 0 CsTAs70 C unless otherwise specified
Parameter
Conditions
Min
Operating Voltage
Power Supply Ripple (Notes 4 5)
Peak to Peak
24
Supply Current
(Note 1)
VCCe2 4V tce64 ms
VCCe5 0V tce16 ms
VCCe5 0V tce4 ms
(tc is instruction cycle time)
HALT Mode Current
(Note 2)
Input Voltage Levels
RESET CKI D0 (clock input)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
VCCe5 0V FINe0 kHz
VCCe2 4V FINe0 kHz
0 9 VCC
0 7 VCC
Input Pull-Up Current
Hi-Z Input Leakage
VCCe4 5V VINe0
b30
b1
Input Capacitance (Note 4)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Output Current Levels (except CKO)
Sink (Note 6)
Source (Standard Option)
Source (Low Current Option)
CKO Current Levels (As Clock Out)
Sink
d4
(d8
d16
Source
d4
(d8
d16
Standard Outputs
VCCe5 0Vg10%
IOHeb100 mA
IOLe400 mA
IOHeb10 mA
IOLe10 mA
VCCe4 5V VOUTeVCC
VCCe2 4V VOUTeVCC
VCCe4 5V VOUTe0V
VCCe2 4V VOUTe0V
VCCe4 5V VOUTe0V
VCCe2 4V VOUTe0V
VCCe4 5V CKIeVCC VOUTeVCC
VCCe4 5V CKIe0V VOUTe0V
27
VCCb0 2
12
02
b0 5
b0 1
b30
b6
03
06
12
b0 3
b0 6
b1 2
Allowable Sink Source Current per Pin
(Note 6)
Allowable Loading on CKO (as HALT)
Current Needed to Over-Ride HALT
(Note 3)
To Continue
To Halt
TRI-STATE or Open Drain
Leakage Current
VCCe4 5V VINe0 2VCC
VCCe4 5V VINe0 7VCC
b2 5
Max
55
0 1 VCC
120
700
3000
40
12
0 1 VCC
0 2 VCC
b330
a1
7
04
02
b330
b80
5
100
07
16
a2 5
Units
V
V
mA
mA
mA
mA
mA
V
V
V
V
mA
mA
pF
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
pF
mA
mA
mA
2
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COP324C COP325C COP326C and COP344C COP345C
Absolute Maximum Ratings
Supply Voltage
6V
Voltage at any Pin
Total Allowable Source Current
Total Allowable Sink Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(soldering 10 seconds)
b0 3V to VCC a 0 3V
25 mA
25 mA
b40 C to a85 C
b65 C to a150 C
300 C
Note Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics b40 CsTAsa85 C unless otherwise specified
Parameter
Conditions
Min
Operating Voltage
Power Supply Ripple (Notes 4 5)
Peak to Peak
30
Supply Current
(Note 1)
VCCe3 0V tce64 ms
VCCe5 0V tce16 ms
VCCe5 0V tce4 ms
(tc is instruction cycle time)
HALT Mode Current
(Note 2)
Input Voltage Levels
RESET CKI DO (clock input)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
VCCe5 0V FINe0 kHz
VCCe3 0V FINe0 kHz
0 9 VCC
0 7 VCC
Input Pull-Up Current
Hi-Z Input Leakage
VCCe4 5V VINe0
b30
b2
Input Capacitance (Note 4)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Output Current Levels (except CKO)
Sink (Note 6)
Source (Standard Option)
Source (Low Current Option)
CKO Current Levels (As Clock Out)
Sink
d4
(d8
d16
Source
d4
(d8
d16
Standard Outputs
VCCe5 0V g10%
IOHeb100 mA
IOLe400 mA
IOHeb10 mA
IOLe10 mA
VCCe4 5V VOUTeVCC
VCCe3 0V VOUTeVCC
VCCe4 5V VOUTe0V
VCCe3 0V VOUTe0V
VCCe4 5V VOUTe0V
VCCe3 0V VOUTe0V
VCCe4 5V CKIeVCC VOUTeVCC
VCCe4 5V CKIe0V VOUTe0V
27
VCCb0 2
12
02
b0 5
b0 1
b30
b8
03
06
12
b0 3
b0 6
b1 2
Allowable Sink Source Current per
Pin (Note 6)
Allowable Loading on CKO (as HALT)
Current Needed to Over-Ride HALT
(Note 3)
To Continue
To Halt
TRI-STATE or Open Drain
Leakage Current
VCCe4 5V VINe0 2VCC
VCCe4 5V VINe0 7VCC
b5
Max
55
0 1 VCC
180
800
3600
60
30
0 1 VCC
0 2 VCC
b440
a2
7
04
02
b440
b200
5
100
09
21
a5
Units
V
V
mA
mA
mA
mA
mA
V
V
V
V
mA
mA
pF
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
pF
mA
mA
mA
3
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COP424C COP425C COP426C and COP444C COP445C
AC Electrical Characteristics 0 CsTAs70 C unless otherwise specified
Parameter
Conditions
Min Max Units
Instruction Cycle Time (tc)
Operating CKI
Frequency
d4 mode
d8 mode
d16 mode
d4 mode
d8 mode
d16 mode
(
(
VCCt4 5V
4 5VlVCCt2 4V
VCCt4 5V
4 5VlVCCt2 4V
4 DC ms
16 DC ms
DC 1 0 MHz
DC 2 0 MHz
DC 4 0 MHz
DC 250 kHz
DC 500 kHz
DC 1 0 MHz
Duty Cycle (Note 4)
Rise Time (Note 4)
Fall Time (Note 4)
Instruction Cycle Time
RC Oscillator (Note 4)
f1e4 MHz
f1e4 MHz External Clock
f1e4 MHz External Clock
Re30k g5% VCC e 5V
Ce82 pF g5% (d4 Mode)
40 60 %
60 ns
40 ns
5 11 ms
Inputs (See Figure 3 )
tSETUP
tHOLD
G Inputs
(SI Input
All Others
VCCt 4 5V
VCCt 4 5V
4 5VlVCCt2 4V
tc 4a 7
03
17
0 25
10
ms
ms
ms
ms
ms
Output Propagation Delay
tPD1 tPD0
tPD1 tPD0
VOUTe1 5V CLe100 pF RLe5k
VCCt 4 5V
4 5VlVCCt2 4V
1 0 ms
4 0 ms
Microbus Timing
Read Operation (Figure 4 )
Chip Select Stable before RD btCSR
Chip Select Hold Time for RD btRCS
RD Pulse WidthbtRR
Data Delay from RD btRD
RD to Data Floating btDF (Note 4)
CLe50 pF VCCe5Vg5%
65 ns
20 ns
400 ns
375 ns
250 ns
Write Operation (Figure 5 )
Chip Select Stable before WR btCSW
Chip Select Hold Time for WR btWCS
WR Pulse WidthbtWW
Data Set-Up Time for WR btDW
Data Hold Time for WR btWD
INTR Transition Time from WR btWI
65 ns
20 ns
400 ns
320 ns
100 ns
700 ns
Note 1 Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI CKO open and all other pins pulled up to VCC with 5k
resistors See current drain equation on page 17
Note 2 The HALT mode will stop CKI from oscillating in the RC and crystal configurations Test conditions all inputs tied to VCC L lines in TRI-STATE mode and
tied to ground all outputs low and tied to ground
Note 3 When forcing HALT current is only needed for a short time (approx 200 ns) to flip the HALT flip-flop
Note 4 This parameter is only sampled and not 100% tested Variation due to the device included
Note 5 Voltage change must be less than 0 5 volts in a 1 ms period
Note 6 SO output sink current must be limited to keep VOL less than 0 2VCC when part is running in order to prevent entering test mode
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COP324C COP325C COP326C and COP344C COP345C
AC Electrical Characteristics b40 CsTAsa85 C unless otherwise specified
Parameter
Conditions
Min Max Units
Instruction Cycle Time (tc)
Operating CKI
Frequency
d4 mode
d8 mode
d16 mode
d4 mode
d8 mode
d16 mode
(
(
VCCt4 5V
4 5VlVCCt3 0V
VCCt4 5V
4 5VlVCCt3 0V
4 DC ms
16 DC ms
DC 1 0 MHz
DC 2 0 MHz
DC 4 0 MHz
DC 250 kHz
DC 500 kHz
DC 1 0 MHz
Duty Cycle (Note 4)
Rise Time (Note 4)
Fall Time (Note 4)
Instruction Cycle Time
RC Oscillator (Note 4)
f1e4 MHz
f1e4 MHz external clock
f1e4 MHz external clock
R e 30k g5% VCC e 5V
C e 82 pF g5% (d4 Mode)
40 60 %
60 ns
40 ns
5 11 ms
Inputs (See Figure 3 )
tSETUP
tHOLD
G Inputs
(SI Inputs
All Others
VCCt 4 5V
VCCt 4 5V
4 5VlVCCt3 0V
tc 4a 7
03
17
0 25
10
ms
ms
ms
ms
ms
Output Propagation Delay
tPD1 tPD0
tPD1 tPD0
VOUTe1 5V CLe100 pF RLe5k
VCCt 4 5V
4 5VlVCCt3 0V
1 0 ms
4 0 ms
Microbus Timing
Read Operation (Figure 4 )
Chip Select Stable before RD btCSR
Chip Select Hold Time for RD btRCS
RD Pulse WidthbtRR
Data Delay from RD btRD
RD to Data Floating btDF (Note 4)
CLe50 pF VCCe5Vg5%
65 ns
20 ns
400 ns
375 ns
250 ns
Write Operation (Figure 5 )
Chip Select Stable before WR btCSW
Chip Select Hold Time for WR btWCS
WR Pulse WidthbtWW
Data Set-Up Time for WR btDW
Data Hold Time for WR btWD
INTR Transition Time from WR btWI
65 ns
20 ns
400 ns
320 ns
100 ns
700 ns
Note 1 Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI CKO open and all other pins pulled up to VCC with 5k
resistors See current drain equation on page 17
Note 2 The HALT mode will stop CKI from oscillating in the RC and crystal configurations Test conditions all inputs tied to VCC L lines in TRI-STATE mode and
tied to ground all outputs low and tied to ground
Note 3 When forcing HALT current is only needed for a short time (approx 200 ns) to flip the HALT flip-flop
Note 4 This parameter is only sampled and not 100% tested Variation due to the device included
Note 5 Voltage change must be less than 0 5 volts in a 1 ms period
Note 6 SO output sink current must be limited to keep VOL less than 0 2VCC when part is running in order to prevent entering test mode
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5