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NB3H83905C
1.8V/2.5V/3.3V Crystal Input
to 1:6 LVTTL/LVCMOS Clock
Fanout Buffer with OE
Description
The NB3H83905C is a 1.8 V, 2.5 V or 3.3 V VDD core Crystal input
to 1:6 LVTTL/LVCMOS fanout buffer with outputs powered by
flexible 1.8 V, 2.5 V, or 3.3 V supply VDDO (with VDD w VDDO). The
device accepts a fundamental Parallel Resonant crystal from 3 MHz to
40 MHz or a singleended LVCMOS Clock from up to 100 MHz.
Two synchronous LVTTL/LVCMOS Enable lines permit
independent control over outputs BCLK[0:4] and output BCLK5;
enabling or disabling only when the output is in LOW state
eliminating potential output glitching or runt pulse generation. When
unused, leave floating open, pins will default to HIGH state.
The 6 outputs drive 50 W series or parallel terminated transmission
lines. Parallel termination should be to 1/2 VCC. Series terminated
lines can drive 2 loads each, or 12 lines total.
Fit, Form, and Function compatible with ICS83905 and PI6C10806.
Features
Six Copies of LVTTL/LVCMOS Output Clock
Supply Operation VDD w VDDO:
1.8 V$0.2 V, 2.5 V $5% or 3.3 V $5% Core VDD
1.8 V$0.2 V, 2.5 V $5%, or 3.3 V $5% Output VDDO
Crystal Oscillator Interface
Crystal Input Frequency Range: 3 MHz to 40 MHz
Clock Input Frequency Range: Up to 100 MHz
LVCMOS compatible Enable Inputs
5 V Tolerant Enable Inputs
Low Output to Output Skew: 80 ps Max
Synchronous Output Enable
Phase Noise Floor 160 dBc (1 MHz)
Industrial Temperature Range
These are PbFree Devices
XTAL_IN/CLK
XTAL_OUT
C1
C2
ENABLE1
ENABLE2
SYNC
SYNC
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
Figure 1. Simplified Block Diagram
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MARKING
DIAGRAMS*
16
SOIC16
D SUFFIX
CASE 751B
NB3H83905G
ALYYWW
1
16
1
TSSOP16
DT SUFFIX
CASE 948F
16
NB3H
905C
ALYWG
G
1
1
QFN20
MN SUFFIX
CASE 485BH
20
1 NB3H
83905
ALYWG
G
A = Assembly Location
L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = PbFree Package
(*Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
November, 2012 Rev. 9
1
Publication Order Number:
NB3H83905C/D

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NB3H83905C
XTAL_OUT 1
16 XTAL_IN/CLK
ENABLE2 2
15 ENABLE1
20 19 18 17 16
GND
BCLK0
VDDO
BCLK1
GND
3
4
5
6
7
14 BCLK5
13 VDDO
12 BCLK4
11 GND
10 BCLK3
GND
GND
BCLK0
VDDO
BCLK1
1
2
3
4
5
EP
6 7 8 9 10
BCLK2
8 9 VDD
SOIC16/TSSOP16
Figure 2. Pinout Configuration (Top View)
QFN20
Exposed Pad
15 BCLK5
14 VDDO
13 BCLK4
12 GND
11 GND
Table 1. PIN DESCRIPTION
SOIC16 /
TSSOP16
QFN20
Name
1 19 XTAL_OUT
2 20 ENABLE 2
3, 7, 11
4, 6, 8,
10, 12, 14
5, 13
1, 2, 6, 7,
11, 12
3, 5, 8,
10, 13, 15
4, 14
GND
BCLK0, 1,
2, 3, 4, 5
VDDO
9 9 VDD
16 NC
15 17 ENABLE 1
16 18 XTAL_IN/
CLK
EP
I/O
Crystal Interface
LVTTL /
LVCMOS Input
GND
LVCMOS
Outputs
POWER
POWER
LVTTL /
LVCMOS Input
Crystal Interface
Description
Oscillator Output to drive Crystal
Synchronous Enable Input for BCLK5 Output. Switches only when
HIGH. Open default condition HIGH due to an internal pullup resistor
to VCC.
GND Supply pins. All GND, VDD and VDDO pins must be externally
connected to power supply to guarantee proper operation.
Buffered Clock Outputs
Positive
must be
Supply voltage for outputs. All
externally connected to power
GsuNpDp,lyVtDoDgaunadraVntDeDeOpproinpser
operation. Bypass with 0.01 mF cap to GND.
Positive Supply voltage for core. All GND, VDD and VDDO pins must
be externally connected to power supply to guarantee proper
operation. Bypass with 0.01 mF cap to GND.
No Connect
Synchronous Enable Input for BCLK0/1/2/3/4 Output block. Switches
only when HIGH. Open default condition HIGH due to an internal
pullup resistor to VCC
Oscillator Input from Crystal. Single ended Clock Input.
The Exposed Pad (EP) on the QFN20 package bottom is thermally
connected to the die for improved heat transfer out of package. The
exposed pad must be attached to a heatsinking conduit. The pad is
not electrically connected to the die, but is recommended to be
electrically and thermally connected to GND on the PC board.
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NB3H83905C
Table 2. CLOCK ENABLE FUNCTION TABLE
Control Inputs
ENABLE1*
ENABLE2*
00
01
10
11
*Defaults HIGH when floating open.
BCLK0:BCLK4
LOW
LOW
Toggling
Toggling
Outputs
BCLK5
LOW
Toggling
LOW
Toggling
BCLK5
BCLK0:4
ENABLE2
ENABLE1
Figure 3. ENABLEx Control Timing Diagram
The ENABLEx control inputs will synchronously enable or disable the selected output(s). This control detects the falling
edge of the internal signal and asserts or deasserts the output after 3 clock cycles. When ENABLEx is LOW, the outputs are
disabled to a LOW state. When ENABLEx is HIGH, the outputs are enabled to toggle.
Table 3. RECOMMENDED CRYSTAL PARAMETERS
Crystal
Fundamental ATCut
Frequency
10 to 40 MHz
Load Capacitance*
1620 pF
Shunt Capacitance, C0
7 pF Max
Equivalent Series Resistance
50 W Max
Drive Level
1 mW
*See APPLICATION INFORMATION; Crystal Input Interface for CL loading
Table 4. ATTRIBUTES (Note 1)
Characteristics
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
> 2 kV
> 200 V
Level 1
UL94 code V0 A 1/8”
28 to 34
213 Devices
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NB3H83905C
Table 5. MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 1
Rating
Unit
VDDx
VI
TA
Tstg
qJA
Positive Power Supply
Input Voltage
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (JunctiontoAmbient)
GND = 0 V
0 lfpm
500 lfpm
SOIC16
SOIC16
4.6
–0.5 v VI v VDD + 0.5
40 to v +85
65 to +150
80
55
V
V
°C
°C
°C/W
qJC Thermal Resistance (JunctiontoCase)
qJA Thermal Resistance (JunctiontoAmbient)
(Note 3)
0 lfpm
500 lfpm
SOIC16
TSSOP16
TSSOP16
3336
138
108
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase)
qJA Thermal Resistance (JunctiontoAmbient)
(Note 3)
0 lfpm
500 lfpm
TSSOP16
QFN20
QFN20
3336
47
33
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase)
(Note 3)
QFN20
18 °C/W
Tsol Wave Solder
3 sec @ 248°C
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board 2S2P (2 signal, 2 power).
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NB3H83905C
Table 6. DC CHARACTERISTICS
Symbol
Characteristic
Min Typ Max Unit
VDD = VDDO = 3.135 V to 3.465 V (3.3 V $5%); GND = 0 V, TA = 405C to +855C
IDD Core Quiescent Power Supply Current (ENABLEx = LOW)
10 mA
IDDO Output Quiescent Power Supply Current (ENABLEx = LOW)
5 mA
VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK
2
VDD +
V
0.3 V
VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK
VOH Output HIGH Voltage (Note 4)
VOL Output LOW Voltage (Note 4)
CIN Input Capacitance
CPD Power Dissipation Capacitance (per Output) (Note 4)
ROUT Output Impedance (Note 4)
VDD = VDDO = 2.375 V to 2.625 V (2.5 V $5%); GND = 0 V, TA = 405C to +855C
IDD Core Quiescent Power Supply Current (ENABLEx = LOW)
0.3
2.6
4
19
7
0.8 V
V
0.5 V
pF
pF
W
8 mA
IDDO Output Quiescent Power Supply Current (ENABLEx = LOW)
4 mA
VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK
1.7
V0D.3DV+
V
VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK
VOH
Output
Output
HIGH
HIGH
Voltage
Voltage
((NIOoHte=4)1
mA)
0.3 0.7 V
2.0 V
1.8
VOL Output LOW Voltage (IOL = 1 mA)
Output LOW Voltage (Note 4)
0.4 V
0.45
CIN Input Capacitance
CPD Power Dissipation Capacitance (per Output) (Note 4)
ROUT Output Impedance (Note 4)
VDD = VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, TA = 405C to +855C
IDD Core Quiescent Power Supply Current (ENABLEx = LOW)
4 pF
18 pF
7W
5 mA
IDDO Output Quiescent Power Supply Current (ENABLEx = LOW)
3 mA
VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK
0.65*VDD
V0D.3DV+
V
VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK
0.3
0.35*VDD
V
VOH Output HIGH Voltage (Note 4)
VDDO0.3
V
VOL Output LOW Voltage (Note 4)
0.35 V
CIN Input Capacitance
4 pF
CPD Power Dissipation Capacitance (per Output) (Note 4)
16 pF
ROUT Output Impedance (Note 4)
10 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Parallel terminated 50 W to VDDO/2 (see Figure 5).
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