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CL-PS7500FE
Advance Data Book
FEATURES
s Available in 56- and 40-MHz speed grades
s System-on-a-chip solution
— 32-bit ARM7 processor with MMU
— 4K unified cache
— FPU (floating point unit)
— Graphics controller drives CRT or LCD
— CD-quality sound audio controller
— DRAM controller
— ROM/Flash controller
— Three-channel DMA for video, cursor, and sound
— PC-style I/O bus
— Two-state power management
— Eight general-purpose I/O lines
s Performance
— 50 Vax-MIPS (Dhrystone®) at 56 MHz
— Up to 12 Mflops, double-precision FP (LINPACK)
s FPU
— Implements ANSI/IEEE Std 754-1985
— Single, double, and extended precision
System-on-a Chip for
Internet Appliance
OVERVIEW
The Cirrus Logic CL-PS7500FE is designed to be
used in internet appliances such as the network
computer, smart-TV, intranet terminal, screen
phones, DVD players, and so on.
The massively integrated CL-PS7500FE offers a
complete system-on-a-chip solution that includes a
32-bit ARM CPU with cache and MMU, CRT and
LCD controller, memory controller, FPU, CD-quality
sound controller, interface to the Cirrus Logic DSP
device for 56K modem and speakerphone, and a
PC-type I/O bus. To handle streaming of audio and
video data on the Internet, the CL-PS7500FE
includes a double-precision FPU to accelerate
software codecs.
Functional
Block Diagram
(cont.)
COLOR LCD SVGA MONITOR
TV HEADPHONES
(cont.)
ROM
DRAM
(4 MBYTE, TYP)
ENCODER
PAL/NTSC
CD-DAC
CS4333
CONFIG. MEMORY
(NON-VOL.)
REALTIME CLOCK
FRONT PANEL:
STATUS LEDs
RUN/STANDBY SW
MEMORY BUS
VIDEO O/P
(RGB)
AUDIO O/P
(32 BIT)
I/O PORT
CL-PS7500FE
240-PIN PQFP
ISA-STYLE
BUS
2 ANALOG
2*PS/2 PORTS
INPUTS
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KEYBOARD
MOUSE
GAMES DEVICE
(ANALOG)
Version 2.0
56k MODEM
CL-MD34XX
ETHERNET
CS89XX
June 1997

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CL-PS7500FE
System-on-a-Chip for Internet Appliance
FEATURES (cont.)
s CRT or color/monochrome LCDs
— Resolutions up to 1024 × 768
— 256-entry 28-bit video palette
— Single- and dual-scan panel LCDs (16-bit grayscale)
s Serial CD digital sound (32-bit) output
s Supports EDO and Fast page mode DRAMs
— Up to 132 Mbytes/sec. (peak) using 64-MHz memory
clock and 32-bit-wide DRAM
— Programmable 16- or 32-bit-wide memory system
— Speed-critical paths are pipelined
s PC-style I/O bus (40-MHz) for connection to any
Cirrus Logic peripheral device
— 56k fax/modem chipset
— CS89XX Ethernet controller
— Can be expanded to 32 bits with external transceivers
s ROM/FLASH
— Supports two 16-Mbyte banks
— Individual read timings
— Burst mode reads
— Allows for writes under register control for FLASH
OVERVIEW (cont.)
The video controller features RGB drive of a SVGA
monitor or a color LCD. It also incorporates various
sync inputs, which when combined with an external
encoder, permit the use of interlaced TV displays.
The device incorporates a digital audio controller
with a 32-bit serial interface for connection to the
Cirrus Logic, CS4333 CD-DAC device. The
CL-PS7500FE can also interface to the Cirrus Logic
56K, FastPathmodem chipset ideal for Internet
access over a POTS line.
The CL-PS7500FE is available in two speed grades:
q ARM CPU running at 40 MHz; memory clock
running up to 64 MHz
q ARM CPU running at 56 MHz; memory clock
running up to 64 MHz
The CL-PS7500FE supports UMA (unified memory
architecture); EDO DRAMs can be used to achieve
high-memory bandwidth.
The CL-PS7500FE is the main computing engine in
the NC platform defined by Oracle®, and runs the
NC operating system and applications.
The device is available in a 240-pin PQFP (plastic
quad flat pack) package.
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ADVANCE DATA BOOK v2.0
June 1997

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CL-PS7500FE
System-on-a-Chip for Internet Appliance
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ADVANCE DATA BOOK v2.0
June 1997

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CL-PS7500FE
System-on-a-Chip for Internet Appliance
TABLE OF CONTENTS
CONVENTIONS.....................................................................................................................12
1. PIN INFORMATION ...............................................................................................................13
1.1 Pin Diagram......................................................................................................................................13
1.2 Block Diagram ..................................................................................................................................14
2. PIN DESCRIPTIONS .............................................................................................................15
2.1 CL-PS7500FE Pin Descriptions .......................................................................................................15
2.2 Power and Ground Pins....................................................................................................................22
2.3 Numerical Pin Listing........................................................................................................................24
3. FUNCTIONAL DESCRIPTION..............................................................................................27
3.1 Functional Block Diagram.................................................................................................................27
3.2 ARM Processor Macrocell ................................................................................................................27
3.3 FPA Macrocell...................................................................................................................................27
3.4 Video and Sound Macrocell..............................................................................................................29
3.5 Clock Control and Power Management ............................................................................................29
3.6 Memory System ...............................................................................................................................29
3.6.1 DMA..................................................................................................................................30
3.6.2 I/O Control ........................................................................................................................30
3.7 Other Features .................................................................................................................................31
3.8 Test Modes .......................................................................................................................................31
3.9 Structure of the CL-PS7500FE.........................................................................................................31
3.9.1 Register Programming......................................................................................................32
3.9.2 Interaction Between Macrocells........................................................................................32
3.10 Resetting CL-PS7500FE Systems ...................................................................................................32
4. THE ARM PROCESSOR MACROCELL ..............................................................................33
4.1 Architecture ......................................................................................................................................33
4.2 Instruction Set ..................................................................................................................................33
4.3 Memory Interface..............................................................................................................................34
4.4 Clocks and Synchronous/Asynchronous Modes ..............................................................................34
5. IDC .........................................................................................................................................35
5.1 Cacheable Bit ...................................................................................................................................35
5.2 IDC Operation...................................................................................................................................35
5.2.1 IDC Validity .......................................................................................................................35
5.2.2 Software IDC Flush...........................................................................................................35
5.2.3 Doubly-Mapped Space .....................................................................................................35
5.2.4 Read-Locked-Write...........................................................................................................36
5.3 IDC Enable/Disable and Reset .........................................................................................................36
5.3.1 Enable the IDC .................................................................................................................36
5.3.2 Disable the IDC.................................................................................................................36
5.4 Write Buffer (WB) .............................................................................................................................36
5.4.1 Bufferable Bit ....................................................................................................................36
5.4.2 Write Buffer Operation ......................................................................................................36
5.4.3 Enable the Write Buffer.....................................................................................................37
www.DataShe5e.4t.44U.coDmisable the Write Buffer ....................................................................................................37
5.5 Coprocessors ...................................................................................................................................37
June 1997
ADVANCE DATA BOOK v2.0
TABLE OF CONTENTS
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
6. ARM PROCESSOR MMU .................................................................................................... 38
6.1 MMU Program-Accessible Registers................................................................................................38
6.1.1 Translation Table Base Register ......................................................................................39
6.1.2 Domain Access Control Register......................................................................................39
6.1.3 Fault Status Register ........................................................................................................39
6.1.4 Fault Address Register .....................................................................................................39
6.2 Address Translation ..........................................................................................................................39
6.3 Translation Process ..........................................................................................................................40
6.3.1 TTB (Translation Table Base)............................................................................................40
6.3.2 Level One Fetch................................................................................................................40
6.3.3 Level One Descriptor ........................................................................................................41
6.3.4 Page Table Descriptor.......................................................................................................41
6.3.5 Section Descriptor ............................................................................................................42
6.4 Translating Section References ........................................................................................................42
6.4.1 Level Two Descriptor.........................................................................................................42
6.5 Translating Small Page References..................................................................................................44
6.6 Translating Large Page References .................................................................................................45
6.7 MMU Faults and CPU Aborts ...........................................................................................................47
6.8 Fault Address and Fault Status Registers (FAR, FSR).....................................................................47
6.9 Domain Access Control ....................................................................................................................48
6.10 Fault-Checking Sequence ................................................................................................................48
6.10.1 Alignment Fault.................................................................................................................49
6.10.2 Translation Fault................................................................................................................50
6.10.3 Domain Fault ....................................................................................................................50
6.10.4 Permission Fault ...............................................................................................................50
6.11 External Aborts.................................................................................................................................50
6.11.1 Interaction of the MMU, IDC, and Write Buffer..................................................................51
7. REGISTER DESCRIPTIONS................................................................................................ 52
7.1 Register Configuration......................................................................................................................52
7.1.1 Big and Little Endian (the Bigend Bit) ...............................................................................52
7.1.2 Configuration Bits for Backward Compatibility ..................................................................53
7.2 Operating Mode Selection ................................................................................................................54
7.3 Registers ..........................................................................................................................................55
7.3.1 PSRs (Program Status Registers) ....................................................................................56
7.4 Exceptions ........................................................................................................................................57
7.4.1 FIQ....................................................................................................................................57
7.4.2 IRQ ...................................................................................................................................58
7.4.3 Abort .................................................................................................................................58
7.4.4 Software Interrupt .............................................................................................................59
7.4.5 Undefined Instruction Trap ................................................................................................60
7.4.6 Vector Summary ...............................................................................................................60
7.4.7 Exception Priorities...........................................................................................................61
7.4.8 Interrupt Latencies............................................................................................................61
7.4.9 Reset ................................................................................................................................61
7.5 Configuration Control Registers .......................................................................................................62
7.5.1 Backward Compatibility ....................................................................................................62
7.5.2 Internal Coprocessor Instructions.....................................................................................62
www.Da7.t5a.3SheeRt4egUis.tceorsm.......................................................................................................................... 63
7.6 Register 1: Control (Write only) ........................................................................................................64
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TABLE OF CONTENTS
ADVANCE DATA BOOK v2.0
June 1997