K4N51163QZ.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 K4N51163QZ 데이타시트 다운로드

No Preview Available !

K4N51163QZ
512M gDDR2 SDRAM
512Mbit gDDR2 SDRAM
84FBGA with Halogen-Free & Lead-Free
(RoHS compliant)
Revision 1.3
September 2008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 of 64
Rev 1.3 September 2008

No Preview Available !

K4N51163QZ
512M gDDR2 SDRAM
Revision History
Revision
1.0
1.1
1.2
Month
December
June
July
Year
2007
2008
2008
1.3 September 2008
History
- Final Spec. released
- Added 1000Mbps speed bin
- Thermal Characteristics on page 10
DC Characteristics on page 9
- Added current data(IDD) for 1000Mbps speed bin
Thermal Characteristics on page 10
- Added values
2 of 64
Rev 1.3 September 2008

No Preview Available !

K4N51163QZ
512M gDDR2 SDRAM
8M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM
with Differential Data Strobe
1.0 FEATURES
• 1.8V + 0.1V power supply for device operation
• 1.8V + 0.1V power supply for I/O interface
• 4 Banks operation
• Posted CAS
• Programmable CAS Letency : 5, 6, 7
• Programmable Additive Latency : 0, 1, 2, 3, 4, 5, 6
• Write Latency (WL) = Read Latency (RL) -1
• Burst Legth : 4 and 8 (Interleave/nibble sequential)
• Programmable Sequential/ Interleave Burst Mode
• Bi-directional Differential Data-Strobe
(Single-ended data-strobe is an optional feature)
• Off-chip Driver (OCD) Impedance Adjustment
• On Die Termination
• Refresh and Self Refresh
Average Refresh Period : 7.8us at lower than TCASE 85 °C,
3.9us at 85 °C < TCASE < 95 °C
• Lead - Free and Halogen - Free 84 ball FBGA (RoHS compliant)
2.0 ORDERING INFORMATION
Part NO.
K4N51163QZ-HC20
K4N51163QZ-HC25
Max Freq.
500MHz
400MHz
Max Data Rate
1000Mbps/pin
800Mbps/pin
VDD/VDDQ
1.8V + 0.1V
Package
84 Ball FBGA
3.0 GENERAL DESCRIPTION
FOR 8M x 16Bit x 4 Bank gDDR2 SDRAM
The 512Mb gDDR2 SDRAM chip is organized as 8Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed
graphic double-data-rate transfer rates of up to 500MHz for general applications. The chip is designed to comply with the following key
gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidi-
rectional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column, and bank
address information in a RAS/CAS multiplexing style. For example, 512Mb(x16) device receive 13/10/2 addressing. The 512Mb gDDR2
devices are available in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
3 of 64
Rev 1.3 September 2008

No Preview Available !

K4N51163QZ
4.0 PIN CONFIGURATION
Normal Package (Top View) : 84ball FBGA Package
512M gDDR2 SDRAM
12 3
789
VDD
NC
VSS
A
VSSQ
UDQS
VDDQ
DQ14
VSSQ
UDM
B
UDQS
VSSQ
DQ15
VDDQ
DQ9
VDDQ
C
VDDQ
DQ8
VDDQ
DQ12
VSSQ
DQ11
D
DQ10
VSSQ
DQ13
VDD
NC
VSS
E
VSSQ
LDQS
VDDQ
DQ6
VSSQ
LDM
F
LDQS
VSSQ
DQ7
VDDQ
DQ1
VDDQ
G
VDDQ
DQ0
VDDQ
DQ4
VSSQ
DQ3
H
DQ2
VSSQ
DQ5
VDDL
VREF
VSS
J VSSDL CK
VDD
CKE WE K RAS CK ODT
NC BA0 BA1 L CAS CS
A10/AP
A1
M
A2
A0 VDD
VSS A3
A5 N A6
A4
A7 A9 P A11 A8 VSS
VDD
A12
NC R NC
NC
Note :
1. VDDL and VSSDL are power and ground for the DLL.
2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.
Ball Locations (x16)
: Populated Ball
+ : Depopulated Ball
Top View
(See the balls through the Package)
123456789
A
B
C
D
E
F
G
H
J
K+
L
M+
N
P+
R
+++
+++
+++
+++
+++
+++
+++
+++
+++
+++
+++
+++
+++
+++
+++
+
+
+
4 of 64
Rev 1.3 September 2008

No Preview Available !

K4N51163QZ
5.0 PACKAGE DIMENSIONS (84 Ball FBGA)
512M gDDR2 SDRAM
MOLDING AREA
(Datum A)
A
(Datum B) B
C
D
E
F
G
H
J
K
L
M
N
P
R
#A1
9.00 ± 0.10
6.40
0.80 1.60
987654321
A # A1 INDEX MARK
B
3.20
(0.95)
(1.80)
9.00 ± 0.10
84-0.45±0.05
0.2 M A B
5 of 64
0.35±0.05
1.10±0.10
Unit : mm
Rev 1.3 September 2008