H5PS5162FFR.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 H5PS5162FFR 데이타시트 다운로드

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H5PS5162FFR Series
512Mb DDR2 SDRAM
H5PS5162FFR-xxC
H5PS5162FFR-xxI
H5PS5162FFR-xxL
H5PS5162FFR-xxJ
[New Product]
H5PS5162FFR-xxP
H5PS5162FFR-xxQ
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1 / Sep. 2010
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H5PS5162FFR series
Revision History
Rev.
1.0
1.1
History
Release
Insert DDR2-1066 & modify DDR2-800 tFAW value
Draft Date
Jul. 2008
Sep. 2010
Rev.1.1 / Sep. 2010
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Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Features
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
H5PS5162FFR series
Rev.1.1 / Sep. 2010
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H5PS5162FFR series
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD ,VDDQ =1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4 / 8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 84ball FBGA(x16) : 8mm x 13mm
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Self-Refresh High Temperature Entry
• Partial Array Self Refresh support
Rev.1.1 / Sep. 2010
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H5PS5162FFR series
Ordering Information
Part No.
H5PS5162FFR-xx*C
H5PS5162FFR-xx*I
Configura-
tion
Power Consumption
Normal Consumption
Normal Consumption
Operation Temp
Commercial
Industrial
Package
H5PS5162FFR-xx*L
H5PS5162FFR-xx*J
H5PS5162FFR-xx*P
H5PS5162FFR-xx*Q
32Mx16
Low Power Consumption
(IDD6 Only)
Low Power Consumption
(IDD6 Only)
Low Current Consumption
Low Current Consumption
Commercial
Industrial
Commercial
Industrial
84 Ball
fBGA
Note:
-XX* is the speed bin, refer to the Operating Frequency table for complete part number.
-xxP and xxQ are the low current bin, refer to the IDD specification table.
- Hynix Halogen-free products are compliant to RoHS.
Hynix supports Lead & Halogen free parts for each speed grade with same specification, except Lead free materials.
We'll add "R" character after "F" for Lead & Halogen free products
Operating Frequency
Grade
E3
C4
Y5
S6
S5
G7
Note:
tCK(ns)
5
3.75
3
2.5
2.5
1.875
CL
3
4
5
6
5
7
tRCD
3
4
5
6
5
7
tRP
3
4
5
6
5
7
Unit
Clk
Clk
Clk
Clk
Clk
Clk
-G7 is a special speed product used in electronic engineering for high speed storage of the working data of a consumer
digital electronic device.
- x16 product only
Rev.1.1 / Sep. 2010
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