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IS61DDPB44M18B/B1/B2
IS61DDPB42M36B/B1/B2
4Mx18, 2Mx36
72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
DECEMBER 2014
FEATURES
DESCRIPTION
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write
operation.
Double Data Rate (DDR) interface for read and
write input ports.
2.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5V to 1.8V VDDQ,
used with 0.75 to 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mm x 15mm & 15mm x 17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
Data Valid Pin (QVLD).
ODT (On Die Termination) feature is supported
optionally on data inputs, K/K#, and BWx#.
The end of top mark (B/B1/B2) is to define options.
IS61DDPB42M36B : Don’t care ODT function
and pin connection
IS61DDPB42M36B1 : Option1
IS61DDPB42M36B2 : Option2
Refer to more detail description at page 6 for each
ODT option.
The 72Mb IS61DDPB42M36B/B1/B2 and
IS61DDPB44M18B/B1/B2 are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have a common I/O bus. The rising
edge of K clock initiates the read/write operation, and all
internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these DDR-IIP (Burst of 4) CIO SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate.
The following are registered internally on the rising edge of
the K clock:
Read/write address
Read enable
Write enable
Byte writes
Data-in for first and third burst addresses
Data-out for second and fourth burst addresses
The following are registered on the rising edge of the K#
clock:
Byte writes
Data-in for second and fourth burst addresses
Data-out for first and third burst addresses
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the third rising
edge of the K# clock (starting two and half cycles later after
read command). The data-outs from the second burst are
updated with the fourth rising edge of the K clock where read
command receives at the first rising edge of K.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/25/2014
1

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IS61DDPB44M18B/B1/B2
IS61DDPB42M36B/B1/B2
Package ballout and description
x36 FBGA Ball Configuration (Top View)
1234
A
CQ# NC/SA1 SA
R/W#
B NC DQ27 DQ18 SA
C NC NC DQ28 VSS
D NC DQ29 DQ19 VSS
E
NC
NC
DQ20
VDDQ
F NC DQ30 DQ21 VDDQ
G NC DQ31 DQ22 VDDQ
H
Doff#
VREF
VDDQ
VDDQ
J
NC
NC
DQ32
VDDQ
K
NC
NC
DQ23
VDDQ
L NC DQ33 DQ24 VDDQ
M NC NC DQ34 VSS
N NC DQ35 DQ25 VSS
P NC NC DQ26 SA
R
TDO TCK
SA
SA
5
BW2#
BW3#
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
6
K#
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
QVLD
ODT
Notes:
The following balls are reserved for higher densities: 2A for 144Mb.
7
BW1#
BW0#
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
8
LD#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
x18 FBGA Ball Configuration (Top View)
1234
A
CQ#
SA
SA R/W#
B
NC DQ9 NC
SA
C NC NC NC VSS
D NC NC DQ10 VSS
E
NC
NC
DQ11
VDDQ
F
NC DQ12 NC
VDDQ
G
NC
NC
DQ13
VDDQ
H
Doff#
VREF
VDDQ
VDDQ
J NC NC NC VDDQ
K
NC
NC
DQ14
VDDQ
L
NC DQ15 NC
VDDQ
M NC NC NC VSS
N NC NC DQ16 VSS
P NC NC DQ17 SA
R
TDO
TCK
SA
SA
5
BW1#
NC/SA1
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
6
K#
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
QVLD
ODT
7
NC/SA1
BW0#
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
8
LD#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
Notes:
1. The following balls are reserved for higher densities: 7A for 144Mb, and 5B for 288Mb.
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ17
NC
DQ15
NC
NC
VREF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/25/2014
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IS61DDPB44M18B/B1/B2
IS61DDPB42M36B/B1/B2
Ball Descriptions
Symbol
K, K#
CQ, CQ#
Doff#
QVLD
SA
DQ0 - DQn
R/W#
LD#
BWx#
VREF
VDD
VDDQ
VSS
ZQ
TMS, TDI, TCK
Type
Input
Output
Input
Output
Input
Bidir
Input
Input
Input
Input
reference
Power
Power
Ground
Input
Input
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
These balls cannot remain VREF level.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals are free running clocks and
do not stop when Q tri-states.
DLL disable and reset input : When low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz.
Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ#.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Data input and output signals. Input data must meet setup and hold times around the rising edges of
K and K# during WRITE operations. These pins drive out the requested data when the read
operation is active. Valid output data is synchronized to the respective CQ and CQ#.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin.
The x36 device uses DQ0~DQ35.
Synchronous Read or Write input. When LD# is low, this input designates the access type (read
when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times
around edge of K.
Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition
includes address and read/write direction.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and K# for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating
Conditions for range.
Ground of the device
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this ball
to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance
mode. This ball cannot be connected directly to VSS or left unconnected.
In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.
The ODT range is selected by ODT control input.
IEEE 1149.1 input pins for JTAG
TDO
NC
ODT
Output
N/A
Input
IEEE 1149.1 input pins for JTAG
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
ODT control; Refer to SRAM features for the details.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/25/2014
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IS61DDPB44M18B/B1/B2
IS61DDPB42M36B/B1/B2
SRAM Features Description
Block Diagram
Data
Register
Burst4
Addresses
19(20)
Add Reg &
Burst
Control
19(20)
LD#
R/W#
BWx#
4(2)
Control
Logic
36(18)
36x4(18x4)
Write
Driver
36x4(18x4)
2M x 36
(4M x 18)
Memory Array
36x4
(18x4)
144
(72)
Output
Reg
36
(18)
36 (18)
DQ(Data-out
&Data-In)
QVLD
CQ, CQ#
(Echo Clocks)
K
K#
Clock
Generator
Select Output Control
/Doff
Note: Numerical values in parentheses refer to the x18 device configuration.
Read Operations
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R/W# in active high
state at the rising edge of the K clock. K and K#, are also used to control the timing to the outputs. The data
corresponding to the first address is clocked two and half cycles later by the rising edge of the K# clock. The data
corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock. A set of free-
running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs. The echo clocks can
be used as data capture clocks by the receiver device.
Whenever LD# is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD# is high)
does not terminate the previous read. The output drivers disable automatically to a high-Z state.
Write Operations
Write operations can also be initiated at every other rising edge of the K clock whenever R/W# is low. The write
address is also registered at that time. When the address needs to change, LD# needs to be low simultaneously to be
registered by the rising edge of K. Again, the write always occurs in bursts of four.
Because of its common I/O architecture, the data bus must be tri-stated at least one cycle before the new data-in is
presented at the DQ bus.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is
presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write
burst address follows next, registered by the rising edge of K#.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
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IS61DDPB44M18B/B1/B2
IS61DDPB42M36B/B1/B2
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array
on the third write cycle. A read cycle to the last two write address produces data from the write buffers. Similarly, a
read address followed by the same write address produces the latest write data. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the two burst addresses is written. (See
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table)
Whenever a write is disabled (R/W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee
impedance matching is between 175Ω and 350Ω at VDDQ=1.5V. The RQ resistor should be placed less than two inches
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ should not be
connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances
values. The final impedance value is achieved within 1024clock cycles.
Valid Data Indicator (QVLD)
A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with
the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle
before the final valid read data arrives.
Delay Locked Loop (DLL)
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy
QUAD mode.
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/25/2014
5