CDP1855, CDP1855C
Functional Description
The CDP1855 is a multiply-divide unit (MDU) designed to be
compatible with CDP1800 series microprocessor systems. It
can, in fact, be interfaced to most 8-bit microprocessors (see
Figure 5). The CDP1855 performs binary multiply or divide
operations as directed by the microprocessor. It can do a
16N-bit by 8N-bit divide yielding a 8N-bit result plus and 8N-
bit remainder. The multiply is an 8N-bit by 8N-bit operation
with a 16N-bit result. The “N” represent the number of
cascaded CDP1855's and can be 1, 2, 3 or 4. All operations
require 8N + 1 shift pulses (See “DELAY NEEDED WITH
AND WITHOUT PRESCALER”).
The CDP1855 contains three registers, X, Y, and Z, which
are loaded with the operands prior to an operation and
contain the results at the completion. In addition, the control
register must be loaded to initiate a multiply or divide. There
is also a status register which contains an overﬂow ﬂag as
shown in the “CONTROL REGISTER BIT ASSIGNMENT
TABLE”. The register address lines (RA0-RA1) are used to
select the appropriate register for loading or reading. The
RD/WE and STB lines are used in conjunction with the RA
lines to determine the exact MDU response (See
“CONTROL TRUTH TABLE”).
When multiple MDU's are cascaded, the loading of each reg-
ister is done sequentially. For example, the ﬁrst selection of
register X for loading loads the most signiﬁcant CDP1855,
the second loads the next signiﬁcant, and so on. Registers
are also read out sequentially. This is accomplished by inter-
nal counters on each MDU which are decremented by STB
during each register selection. When the counter matches
the chip number (CN1, CN0 lines), the device is selected.
These counters must be cleared with a clear on pin 2 or with
bit 6 in the control word (See “CONTROL REGISTER BIT
ASSIGNMENT TABLE”) in order to start each sequence of
accesses with the most signiﬁcant device.
The CDP1855 has a built in clock prescaler which can be
selected via bit 7 in the control register. The prescaler may
be necessary in cascaded systems operating at high
frequencies or in systems where a suitable clock frequency
is not readily available. Without the prescaler select, the shift
frequency is equal to the clock input frequency. With the
prescaler selected, the rate depends on the number of
MDU's as deﬁned by bits 4 and 5 of the control word (See
“CONTROL REGISTER BIT ASSIGNMENT TABLE”).
1. For one MDU, the clock frequency is divided by 2.
2. For two MDU's the clock frequency is divided by 4.
3. For 3 or 4 MDU's, the clock frequency is divided by 8.
Operation
1. Initialization and Controls
The CDP1855 must be cleared by a low on pin 2 during
power-on which prevents bus contention problems at the YL,
YR and ZL, ZR terminals and also resets the sequence
counters and the shift pulse generator.
Prior to loading any other registers the control register must
be loaded to specify the number of MDU's being used (See
“CONTROL REGISTER BIT ASSIGNMENT TABLE”).
Once the number of devices has been speciﬁed and the
sequence counters cleared with a clear pulse or bit 6 of the
control word, the X, Y, and Z registers can be loaded as
deﬁned in the “CONTROL TRUTH TABLE”. All bytes of the X
register can be loaded, then all bytes of the Y, and then all
bytes of the Z, or they can be loaded randomly. Successive
loads to a given register will always proceed sequentially
from the most signiﬁcant byte to the least signiﬁcant byte, as
previously described. Resetting the sequence counters
select the most signiﬁcant MDU. In a four MDU system, load-
ing all MDU's results in the sequence counter pointing to the
ﬁrst MDU again. In all other conﬁgurations (1, 2, or 3
MDU's), the sequence counter must be reset prior to each
series of register reads or writes.
2. Divide Operation
For the divide operation, the divisor is loaded in the X
register. The dividend is loaded in the Y and Z registers with
the more signiﬁcant half in the Y register and the less signiﬁ-
cant half in the Z register. These registers may be loaded in
any order, and after loading is completed, a control word is
loaded to specify a divide operation and the number of
MDU's and also to reset the sequence counters and Y or Z
register and select the clock option if desired. Clearing the
sequence counters with bit 6 will set the MDU's up for read-
ing the results.
The X register will be unaltered by the operation. The
quotient will be in the Z register while the remainder will be in
the Y register. An overﬂow will be indicated by the C.O./O.F.
of the most signiﬁcant MDU and can also be determined by
reading the status byte.
While the CDP1855 is speciﬁed to perform 16 by 8-bit
divides, if the quotient of a divide operation exceeds the size
of the Z register(s) (8N-bits - where N is the number of
cascaded CDP1855's) the overﬂow bit in the Status Register
will be set. Neither the quotient in Z nor the remainder in Y
will represent a valid answer. This will always be the result of
a division performed when the divisor (X) is equal to or less
than the most signiﬁcant 8N-bits of the dividend (Y).
The MDU can still be used for such computations if the
divide is done in two steps. The dividend is split into two
parts-the more signiﬁcant 8N-bits and the less signiﬁcant
8N-bits-and a divide done on each part. Each step yields an
8N-bit result for a total quotient of 16N-bits.
The ﬁrst step consists of dividing the more signiﬁcant 8N-
bits by the divisor. This is done by clearing the Y register(s),
loading the Z register(s) with the more signiﬁcant 8N-bits of
the dividend, and loading the X register(s) with the divisor. A
division is performed and the resultant value in Z represents
the more signiﬁcant 8N-bits of the ﬁnal quotient. The Z regis-
ter(s) value must be unloaded and saved by the processor.
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