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March 1997
CDP1855,
CDP1855C
8-Bit Programmable
Multiply/Divide Unit
Features
• Cascadable Up to 4 Units for 32-Bit by 32-Bit Multiply
÷or 64 32-Bit Divide
÷• 8-Bit by 8-Bit Multiply or 16 8-Bit Divide in 5.6µs at
5V or 2.8µs at 10V
• Direct Interface to CDP1800-Series Microprocessors
• Easy Interface to Other 8-Bit Microprocessors
• Significantly Increases Throughput of Microprocessor
Used for Arithmetic Calculations
Ordering Information
PACKAGE TEMP. RANGE
5V
PDIP
-40oC to +85oC CDP1855CE
PKG.
10V NO.
CDP1855E E28.6
Burn-In
SBDIP
CDP1855CEX - E28.6
-40oC to +85oC CDP1855CD CDP1855D D28.6
Burn-In
CDP1855CDX - D28.6
Description
The CDP1855 and CDP1855C are CMOS 8-bit multi-
ply/divide units which can be used to greatly increase the
capabilities of 8-bit microprocessors. They perform multiply
and divide operations on unsigned, binary operators. In
general, microprocessors do not contain multiply or divide
instructions and even efficiently coded multiply or divide
subroutines require considerable memory and execution
time. These multiply/divide units directly interface to the
CDP1800-series microprocessors via the N-lines and can
easily be configured to fit in either the memory or I/O space
of other 8-bit microprocessors.
The multiple/divide unit is based on a method of multiplying
by add and shift right operations and dividing by subtract and
shift left operations. The device is structured to permit cas-
cading identical units to handle operands up to 32 bits.
The CDP1855 and CDP1855C are functionally identical.
They differ in that the CDP1855 has a recommended
operating voltage range of 4V to 10.5V, and the CDP1855C,
a recommended operating voltage range of 4V to 6.5V.
The CDP1855 and CDP1855C types are supplied in a 28
lead hermetic dual-in-line ceramic package (D suffix) and in
a 28 lead dual-in-line plastic package (E suffix). The
CDP1855C is also available in chip form (H suffix).
Pinout
28 LEAD DIP
TOP VIEW
Circuit Configuration
+V
CE 1
CLEAR 2
CTL 3
C.O./O.F. 4
YL 5
ZL 6
SHIFT 7
CLK 8
STB 9
RD/WE 10
RA2 11
RA1 12
RA0 13
VSS 14
28 VDD
27 CN0
26 CN1
25 CI
24 YR
23 ZR
22 BUS 7
21 BUS 6
20 BUS 5
19 BUS 4
18 BUS 3
17 BUS 2
16 BUS 1
15 BUS 0
CLEAR
XTAL
N0
N1
N2
TPB
MRD
CDP1802
EF
BUS
CLEAR
CLK
CE
RA0
C1
RA1
CN0
RA2
CN1
STB
RD/WE
CDP1855
YL
ZR
CTL
C0
YR
ZL
BUS
FIGURE 1. MDU ADDRESSED AS I/O DEVICE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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File Number 1053.2

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CDP1855, CDP1855C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All voltage values referenced to VSS terminal)
CDP1855 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1855C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
55
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
50
12
Device Dissipation Per Output Transistor
For TA = Full Package-Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA) . . . . . . . . . . . . .-40oC to +85oC
Storage Temperature Range (TSTg) . . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Static Electrical Specifications At TA = -40 to +85oC, VDD ±10%, Unless Otherwise Specified
CONDITIONS
LIMITS
CDP1855
CDP1855C
PARAMETER
VO VIN VDD
(NOTE1)
(NOTE1)
(V) (V) (V) MIN TYP MAX MIN TYP MAX UNITS
Quiescent Device
Current
IDD
- 0, 5 5
-
0.01 50
-
0.02 200 µA
- 0, 10 10
-
1 200 -
- - µA
Output Low Drive (Sink) IOL 0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - mA
Current
0.5 0, 10 10
2.6
5.2
-
-
- - mA
Output High Drive
(Source) Current
IOH 4.6 0, 5 5 -1.15 -2.3
9.5 0, 10 10 -2.6
-5.2
- -1.15 -2.3
--
-
- mA
- mA
Output Voltage Low Level VOL
-
0, 5 5
-
(Note 2)
- 0, 10 10
-
0 0.1 -
0 0.1 -
0 0.1 V
- -V
Output Voltage High Level VOH - 0, 5 5 4.9 5 - 4.9 5 - V
(Note 2)
-
0, 10 10
9.9
10
-
-
- -V
Input Low Voltage
VIL 0.5, 4.5
-
5
-
0.5, 9.5
-
10
-
- 1.5 -
- 3-
- 1.5 V
- -V
Input High Voltage
VIH 0.5, 4.5
-
5 3.5
-
- 3.5
-
-V
0.5, 9.5
-
10
7
- --
- -V
Input Leakage Current
IIN - 0, 5 5 -
- 0, 10 10
-
- ±1 -
- ±1 -
- ±1 µA
- - µA
Three-State Output
Leakage Current
IOUT
0, 5
0, 10
0, 5
0, 10
5
10
-
-
- ±1 -
- ±10 -
- ±1 µA
- - µA
Operating Current
(Note 3)
IDD1
-
0, 5 5
-
- 0, 10 10
-
1.5 - -
6 12 -
1.5 3 mA
- - mA
Input Capacitance
CIN -
--
Output Capacitance
COUT
-
--
NOTES:
1. Typical values are for TA = +25oC and nominal VDD.
2. IOL = IOH = 1µA
3. Operating current is measured at 3.2MHz with open outputs.
-
-
5 7.5 -
10 15 -
5 7.5 pF
10 15 pF
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CDP1855, CDP1855C
Recommended Operating Conditions At TA = Full package temperature range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
LIMITS
PARAMETER
VDD
(V)
CDP1855
MIN MAX
CDP1855C
MIN MAX
UNITS
DC Operating Voltage Range
- 4 10.5 4 6.5 V
Input Voltage Range
Maximum Clock Input Frequency
-
VSS
VDD
VSS
VDD
V
5 3.2 - 3.2 - MHz
10 6.4
-
-
- MHz
Minimum 8 x 8 Multiply (16 ÷ 8 Divide) Time
5 - 5.6 - 5.6 µs
10 - 2.8 -
- µs
CE RA2 RA1 RA0
1 11 12 13
REGISTER
SELECT LOGIC
SELECT CONTROL
SELECT Z
SELECT Y
SELECT X
X SEQUENCE
COUNTER
RESET OUT
SELECT STATUS
X REGISTER
LOAD
CLOCK
8
CN1
26
CN0
27
CHIP
NO.
8
SHIFT
GENERATOR
8
ADD/
SUBTRACT
8 C.O.
STATUS
REG
25 C.I.
3 CTL.
4 C.O./O.F.
Y SEQUENCE
COUNTER
RESET OUT
SHIFT Y REGISTER
LOAD RESET
8
5 YL
24 YR
Z SEQUENCE
COUNTER
RESET OUT
SHIFT Z REGISTER
LOAD RESET
8
6 ZL
23 ZR
LOAD
BUS BUS BUS BUS BUS BUS BUS BUS
76543 2 1 0
22 21 20 19 18 17 16 15
9
27
10 14 VSS
STB
CLEAR SHIFT
RD/WE
28 VDD
FIGURE 2. BLOCK DIAGRAM OF CDP1855 AND CDP1855C
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CDP1855, CDP1855C
Functional Description
The CDP1855 is a multiply-divide unit (MDU) designed to be
compatible with CDP1800 series microprocessor systems. It
can, in fact, be interfaced to most 8-bit microprocessors (see
Figure 5). The CDP1855 performs binary multiply or divide
operations as directed by the microprocessor. It can do a
16N-bit by 8N-bit divide yielding a 8N-bit result plus and 8N-
bit remainder. The multiply is an 8N-bit by 8N-bit operation
with a 16N-bit result. The “N” represent the number of
cascaded CDP1855's and can be 1, 2, 3 or 4. All operations
require 8N + 1 shift pulses (See “DELAY NEEDED WITH
AND WITHOUT PRESCALER”).
The CDP1855 contains three registers, X, Y, and Z, which
are loaded with the operands prior to an operation and
contain the results at the completion. In addition, the control
register must be loaded to initiate a multiply or divide. There
is also a status register which contains an overflow flag as
shown in the “CONTROL REGISTER BIT ASSIGNMENT
TABLE”. The register address lines (RA0-RA1) are used to
select the appropriate register for loading or reading. The
RD/WE and STB lines are used in conjunction with the RA
lines to determine the exact MDU response (See
“CONTROL TRUTH TABLE”).
When multiple MDU's are cascaded, the loading of each reg-
ister is done sequentially. For example, the first selection of
register X for loading loads the most significant CDP1855,
the second loads the next significant, and so on. Registers
are also read out sequentially. This is accomplished by inter-
nal counters on each MDU which are decremented by STB
during each register selection. When the counter matches
the chip number (CN1, CN0 lines), the device is selected.
These counters must be cleared with a clear on pin 2 or with
bit 6 in the control word (See “CONTROL REGISTER BIT
ASSIGNMENT TABLE”) in order to start each sequence of
accesses with the most significant device.
The CDP1855 has a built in clock prescaler which can be
selected via bit 7 in the control register. The prescaler may
be necessary in cascaded systems operating at high
frequencies or in systems where a suitable clock frequency
is not readily available. Without the prescaler select, the shift
frequency is equal to the clock input frequency. With the
prescaler selected, the rate depends on the number of
MDU's as defined by bits 4 and 5 of the control word (See
“CONTROL REGISTER BIT ASSIGNMENT TABLE”).
1. For one MDU, the clock frequency is divided by 2.
2. For two MDU's the clock frequency is divided by 4.
3. For 3 or 4 MDU's, the clock frequency is divided by 8.
Operation
1. Initialization and Controls
The CDP1855 must be cleared by a low on pin 2 during
power-on which prevents bus contention problems at the YL,
YR and ZL, ZR terminals and also resets the sequence
counters and the shift pulse generator.
Prior to loading any other registers the control register must
be loaded to specify the number of MDU's being used (See
“CONTROL REGISTER BIT ASSIGNMENT TABLE”).
Once the number of devices has been specified and the
sequence counters cleared with a clear pulse or bit 6 of the
control word, the X, Y, and Z registers can be loaded as
defined in the “CONTROL TRUTH TABLE”. All bytes of the X
register can be loaded, then all bytes of the Y, and then all
bytes of the Z, or they can be loaded randomly. Successive
loads to a given register will always proceed sequentially
from the most significant byte to the least significant byte, as
previously described. Resetting the sequence counters
select the most significant MDU. In a four MDU system, load-
ing all MDU's results in the sequence counter pointing to the
first MDU again. In all other configurations (1, 2, or 3
MDU's), the sequence counter must be reset prior to each
series of register reads or writes.
2. Divide Operation
For the divide operation, the divisor is loaded in the X
register. The dividend is loaded in the Y and Z registers with
the more significant half in the Y register and the less signifi-
cant half in the Z register. These registers may be loaded in
any order, and after loading is completed, a control word is
loaded to specify a divide operation and the number of
MDU's and also to reset the sequence counters and Y or Z
register and select the clock option if desired. Clearing the
sequence counters with bit 6 will set the MDU's up for read-
ing the results.
The X register will be unaltered by the operation. The
quotient will be in the Z register while the remainder will be in
the Y register. An overflow will be indicated by the C.O./O.F.
of the most significant MDU and can also be determined by
reading the status byte.
While the CDP1855 is specified to perform 16 by 8-bit
divides, if the quotient of a divide operation exceeds the size
of the Z register(s) (8N-bits - where N is the number of
cascaded CDP1855's) the overflow bit in the Status Register
will be set. Neither the quotient in Z nor the remainder in Y
will represent a valid answer. This will always be the result of
a division performed when the divisor (X) is equal to or less
than the most significant 8N-bits of the dividend (Y).
The MDU can still be used for such computations if the
divide is done in two steps. The dividend is split into two
parts-the more significant 8N-bits and the less significant
8N-bits-and a divide done on each part. Each step yields an
8N-bit result for a total quotient of 16N-bits.
The first step consists of dividing the more significant 8N-
bits by the divisor. This is done by clearing the Y register(s),
loading the Z register(s) with the more significant 8N-bits of
the dividend, and loading the X register(s) with the divisor. A
division is performed and the resultant value in Z represents
the more significant 8N-bits of the final quotient. The Z regis-
ter(s) value must be unloaded and saved by the processor.
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CDP1855, CDP1855C
A second division is performed using the remainder from the
first division (in Y) as the more significant 8N-bits of the divi-
dend and the less significant half of the original dividend
loaded into the Z register. The divisor in X remains unaltered
and is, by definition, larger than the remainder from the first
division which is in Y. The resulting value in Z becomes the
less significant 8N-bits of the final quotient and the value in Y
is, as usual, the remainder.
Extending this technique to more steps allows division of any
size number by an 8N-bit divisor.
Note that division by zero is never permitted and must be
tested for and handled in software.
The following example illustrates the use of this algorithm.
Example:
Assume three MDU's capable of a by 24-bit division. The
problem is to divide 00F273, 491C06H by 0003B4H.
Step 1: 000000 , 00F273 / 0003B4 = 000041 R=0001BF
Y Z(MS)
X
Z1 Y1
Step 2: 0001BF , 491C06 / 0003B4 = 78C936 R=00000E
Y1 Z(LS)
X
Z2 Y2
Result: 000041 , 78C936
R=00000E
Z1 Z2
Y2
The Z register can simply be reset using bit 2 of the control
word and another divide can be done in order to further
divide the remainder.
3. Multiply Operation
For a multiply operation the two numbers to be multiplied are
loaded in the X and Z registers. The result is in the Y and Z
register with Y being the more significant half and Z the less
significant half. The X register will be unchanged after the
operation is completed.
The original contents of the Y register are added to the
product of X and Z. Bit 3 of the control word will reset
register Y to 0 if desired.
Functional Description of
CDP1855 Terminals
CE - Chip Enable (Input):
A high on this pin enables the CDP1855 MDU to respond to
the select lines. All cascaded MDU's must be enabled
together. CE also controls the three-state C.O./O.F., output
of the most significant MDU.
Clear (Input):
The CDP1855 MDU(s) must be cleared upon power-on with
a low-on this pin. The clear signal resets the sequence
counters, the shift pulse generator, and bits 0 and 1 of the
control register.
CTL - Control (Input):
This is an input pin. All CTL pins must be wired together and
to the YL of the most significant CDP1855 MDU and to the
ZR of the least significant CDP1855 MDU. This signal is
used to indicate whether the registers are to be operated on
or only shifted.
C.O./O.F. - Carry Out/Over Flow (Output):
This is a three-state output pin. It is the CDP1855 Carry Out
signal and is connected to Cl (CARRY-IN) of the next more
significant CDP1855 MDU, except for on the most significant
MDU. On that MDU it is an overflow indicator and is enabled
when chip enables is true. A low on this pin indicates that an
overflow has occurred. The overflow signal is latched each
time the control register is loaded, but is only meaningful
after a divide command.
YL, YR - Y-Left, Y-Right:
These are three-state bi-directional pins for data transfer
between the Y registers of cascaded CDP1855 MDU's. The
YR pin is an output and YL is an input during a multiply and
the reverse is true at all other times. The YL pin must be
connected to the YR pin of the next more significant MDU.
An exception is that the YL pin of the most significant
CDP1855 MDU must be connected to the ZR pin of the least
significant MDU and to the CTL pins of all MDU's. Also the
YR pin of the least significant MDU is tied to the ZL pin of the
most significant MDU.
ZL, ZR - Z-Left, Z-Right:
These are three-state bi-directional pins for data transfers
between the “Z” registers of cascaded MDU's. The ZR pin is
an output and ZL is an input during a multiply and the
reverse is true at all other times. The ZL pin must be tied to
the YR pin of the next more significant MDU. An exception is
that the ZL in of the most significant MDU must be con-
nected to the YR pin of the least significant MDU. Also, the
ZR pin of the least significant MDU is tied to the YL of the
most significant MDU.
Shift - Shift Clock:
This is a three-state bi-directional pin. It is an output on the
most significant MDU. And an input on all other MDU's. It
provides the MDU system timing pulses. All SHIFT pins must
be connected together for cascaded operation. A maximum
of the 8N +1 shifts are required for an operation where "N"
equals the number of MDU devices that are cascaded.
CLK - Clock (Input):
This pin should be grounded on all but the most significant
MDU. There is an optional reduction of clock frequency avail-
able on this pin if so desired, controlled by bit 7 of the control
byte.
STB - Strobe (Input):
When RD/WE is low, data is latched from bus lines on the
falling edge of this signal. It may be asynchronous to the
clock. Strobe also increments the selected register's
sequence counter during reads and writes. TPB would be
used in CDP1800 systems.
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