HD74LS73A.pdf 데이터시트 (총 7 페이지) - 파일 다운로드 HD74LS73A 데이타시트 다운로드

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HD74LS73A
Dual J-K Flip-Flops (with Clear)
Features
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS73AP
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
HD74LS73ARPEL SOP-14 pin (JEDEC)
PRSP0014DE-A
(FP-14DNV)
RP
Note: Please consult the sales office for the above package availability.
Pin Arrangement
REJ03D0414–0300
Rev.3.00
Jul.22.2005
Taping Abbreviation
(Quantity)
EL (2,500 pcs/reel)
1CK 1
1CLR 2
1K 3
VCC
2CK
4
5
2CLR 6
2J 7
CLR
JQ
CK
KQ
KQ
CK
JQ
CLR
(Top view)
14 1J
13 1Q
12 1Q
11 GND
10 2K
9 2Q
8 2Q
Function Table
Inputs
Outputs
Clear
Clock
J
K
QQ
L XX X LH
H L L Q0 Q0
HH L HL
HLHLH
HHH
Toggle
H H X X QO
H; high level, L; low level, X; irrelevant, ; transition from high to low level,
Q0; level of Q before the indicated steady-state input conditions were established.
Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by .
QO
Rev.3.00, Jul.22.2005, page 1 of 6

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HD74LS73A
Block Diagram (1/2)
QQ
Clear
KJ
Clock
Absolute Maximum Ratings
Item
Symbol
Ratings
Supply voltage
VCC
7
Input voltage
VIN 7
Power dissipation
PT 400
Storage temperature
Tstg –65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
Supply voltage
VCC
Output current
IOH
IOL
Operating temperature
Topr
Clock frequency
fclock
Pulse width
tw (Clock High)
tw (Clear Low)
Setup time
tsu (“H” Data)
tsu (“L” Data)
Hold time
th
Note: ; The arrow indicates the falling edge.
Min
4.75
–20
0
20
25
20
20
0
Typ
5.00
25
Max
5.25
–400
8
75
30
Unit
V
V
mW
°C
Unit
V
µA
mA
°C
MHz
ns
ns
ns
Rev.3.00, Jul.22.2005, page 2 of 6

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HD74LS73A
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Symbol min. typ.* max. Unit
Condition
Input voltage
Output voltage
J, K
VIH 2.0 — — V
VIL — — 0.8 V
VOH
2.7 —
V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
VOL
— — 0.5 V IOL = 8 mA VCC = 4.75 V, VIH = 2 V,
— — 0.4
IOL = 4 mA VIL = 0.8 V
— — 20
Clear
IIH — — 60 µA VCC = 5.25 V, VI = 2.7 V
Clock
— — 80
J, K — — –0.4
Input current
Clear
IIL — — –0.8 mA VCC = 5.25 V, VI = 0.4 V
Clock
— — –0.8
J, K — — 0.1
Clear
II — — 0.3 mA VCC = 5.25 V, VI = 7 V
Clock
— — 0.4
Short-circuit output current
IOS –20 — –100 mA VCC = 5.25 V
Supply current**
ICC
—4
6 mA VCC = 5.25 V
Input clamp voltage
VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** With all outputs open, ICC is measured with the Q and Q outputs high in turn. At time of measurement, the
clock input is founded.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Symbol Inputs Outputs min. typ. max. Unit
Condition
Maximum clock frequency
Propagation delay time
fmax
tPLH
tPHL
30 45 — MHz
Clear Q, Q — 15 20 ns CL = 15 pF, RL = 2 k
Clock
— 15 20 ns
Timing Definition
tw
Clock
J, K
1.3 V
tsu
1.3 V
th
1.3 V
"H" Data
1.3 V
1.3 V
tsu th
"L" Data
1.3 V
3V
0V
3V
0V
Rev.3.00, Jul.22.2005, page 3 of 6

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HD74LS73A
Testing Method
Test Circuit
1. ƒmax, tPLH, tPHL, (ClockQ, Q)
Input 4.5V
VCC Output Q
P.G.
Zout=50
J
CK
K
CLR
Q
Output Q
Q
Load circuit 1
RL
CL
Same as Load Circuit 1.
Notes:
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
2. tPHL (ClearQ), tPLH (ClearQ)
VCC Output Q
P.G.
Zout=50
P.G.
Zout=50
4.5V
Input
Input
J
CK
K
CLR
Q
Output Q
Q
Load circuit 1
RL
CL
Same as Load Circuit 1.
Notes:
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
Rev.3.00, Jul.22.2005, page 4 of 6

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HD74LS73A
Waveforms 1
Clock
Q
10%
tTLH
tTHL
90% 90%
1.3 V 1.3 V
tw(H)
tw(L)
10%
tPLH
1.3 V 1.3 V
tPHL
1.3 V
tPHL
1.3 V
tPLH
3V
0V
VOH
VOL
Note:
Q VOH
1.3 V
1.3 V
VOL
Clock input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax,
tTLH = tTHL 2.5 ns
Waveforms 2
Clear
Clock
Q
tTHL
tTLH
90%
1.3V
10%
tw (CLR)
90%
1.3V
10%
tPHL
tTLH
tTHL
10%
90% 90%
1.3V 1.3V
tw (CK) 20ns
10%
1.3V
tPLH
1.3V
Q
Note: Crear and clock input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz,
3V
0V
3V
0V
VOH
VOL
VOH
VOL
Rev.3.00, Jul.22.2005, page 5 of 6