CGS702V.pdf 데이터시트 (총 10 페이지) - 파일 다운로드 CGS702V 데이타시트 다운로드

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September 1995
CGS702V
Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
with Improved EMI
General Description
The CGS702 is an off-the-shelf clock driver specifically de-
signed for today’s high speed processors It provides low
skew outputs which are produced at different frequencies
from three fixed input references The CGS702 is a reduced
EMI version of the CGS700 The XTALIN input pin is de-
signed to be driven from three distinct crystal oscillators run-
ning at 25 MHz 33 MHz or 40 MHz
The PLL using a charge pump and an internal loop filter
multiplies this input frequency to create a maximum output
frequency of four times the input
The device includes a TRI-STATE control pin to disable
the outputs while the PLL is still in lock This function allows
testing the board without having to wait to acquire the lock
once the testing is complete
(Continued)
Features
Y Reduced EMI compared to CGS700 (refer to EMI
characteristics)
Y Guaranteed and tested 500 ps pin-to-pin skew (TOSHL
and TOSLH) on 1x outputs
Y PentiumTM and PowerPCTM compatible
Y Output buffer of nine drivers for large fanout
Y 25 MHz – 160 MHz output frequency range
Y Outputs operating at 4x 2x 1x of the reference
frequency for multi-frequency bus applications
Y Selectable output frequency
Y Internal loop filter to reduce noise and jitter
Y Separate Analog and digital VCC and Ground pins
Y Low frequency test mode by disabling the PLL
Y Implemented on National’s Core CMOS process
Y Symmetric output current drive
a30 mA b30 mA IOL IOH
Y 28-pin PCC for optimum skew performance
Y Guaranteed 2 kV ESD protection
Connection Diagram
Pin Assignment for PLCC
TL F 12386 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
PentiumTM is a trademark of Intel Corporation
PowerPCTM is a trademark of International Business Machines Corporation
Pin Description
PLCC Package
Pin Name
Description
1 VCC
2 SKWSEL
Digital VCC
Skew Test Selector Pin
3 CLK4
4x Clock Output
4 VCC
5 XTALIN
Digital VCC
Crystal Oscillator Input
6 GND
Digital Ground
7 CLK1 0
1x Clock Output
8 VCC
9 CLK1 1
Digital VCC
1x Clock Output
10 GND
Digital Ground
11 CLK1 2
1x Clock Output
12 TRI-STATE Output TRI-STATE Control
13 SKWTST
Skew Testing Pin
14 CLK1 3
1x Clock Output
15 GND
Digital Ground
16 CLK1 4
1x Clock Output
17 VCC
18 EXTCLK
Digital VCC
External Test Clock
19 GNDA
Analog Ground
20 VCCA
21 EXTSEL
Analog VCC
External Clock MUX Selector
22 GND
Digital Ground
23 CLK1 5
1x Clock Output
24 VCC
25 CLK1 6
Digital VCC
1x Clock Output
26 CLK1SEL
CLK1 Multiplier Selector
27 GND
Digital Ground
28 CLK2
2x Clock Output
C1995 National Semiconductor Corporation TL F 12386
RRD-B30M105 Printed in U S A

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General Description (Continued)
Also included are two EXTSEL and EXTCLK pins to allow
testing the chip via an external source The EXTSEL pin
once set to high causes the External-Clock Mux to
change its input from the output of the VCO and Counter to
the external clock signal provided via EXTCLK input pin
CLK1SEL pin changes the output frequency of the CLK1
0 6 outputs During normal operation when CLK1SEL pin is
high these outputs are at the same frequency as the input
crystal oscillator while CLK2 and CLK4 outputs are at twice
and four times the input frequency respectively
Block Diagram
Once CLK1SEL pin is set to a low logic level the CLK1
outputs will be at twice the input frequency the same as the
CLK2 output with CLK4 output still being at four times the
input frequency
In addition two other pins are added for increasing the test
capability SKWSEL and SKWTST pins allow testing of the
counter’s output and skew of the output drivers by bypass-
ing the VCO In this test mode CLK4 frequency is the same
as SKWTST input frequency while CLK2 is and CLK1
frequencies are respectively (refer to the truth table) In
addition CLK1SEL functionality is also true under this test
condition
TL F 12386 – 2
2

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Truth Table
Input
CLK1 EXT EXT SKW
SEL SEL CLK SEL
H LX L
L LX L
XH
X
H LXH
L LXH
X XX X
Steady state phase frequency lock
SKW
TST
X
X
X
X
TRI-
STATE
H
H
H
H
H
L
CLK4
4x fIN
4x fIN
1x fTST
1x fTST
Z
Typical Application
Output
CLK2
2x fIN
2x fIN
x fTST
x fTST
Z
CLK1
fIN
2x fIN
x fTST
x fTST
Z
TL F 12386 – 3
3

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Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
b0 5V to 7 0V
DC Input Voltage Diode Current (IIK)
V e b0 5V
b20 mA
V e VCC a 0 5V
a20 mA
DC Input Voltage (VI)
b0 5V to VCC a 0 5V
DC Output Diode Current (IO)
V e b0 5V
b20 mA
V e VCC a 0 5V
a20 mA
DC Output Voltage (VO)
b0 5V to VCC a 0 5V
DC Output Source
or Sink Current (IO)
g60 mA
DC VCC or Ground Current
per Output Pin (ICO or IGND)
g60 mA
Storage Temperature (TSTG)
b65 C to a150 C
Junction Temperature
150 C
Power Dissipation (Static and Dynamic) (Note 2) 1400 mW
Note 1 The Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed The device should not
be operated at these limits The parametric values defined in the
DC and AC Electrical Characteristics tables are not guaranteed at
the Absolute Maximum Ratings The Recommended Operating
Conditions will define the conditions for actual device operation
Note 2 Power dissipation is calculated using 49 W as the thermal coeffi-
cient for the PCC package at 225 LFM airflow The input frequency
is assumed at 33 MHz with CLK4 at 132 MHz and CLK2 and
CLK1’s being at 66 MHz In addition the ambient temperature is
assumed 70 with power supply at 5 0V
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Input Crystal Frequency
4 5V to 5 5V
0V to VCC
0V to VCC
25 MHz – 40 MHz
Operating Temperature (TA)
External Clock Frequency (EXTCLK Pin)
0 C to a70 C
1 MHz – 10 MHz
XTALIN Duty Cycle Range
25 75 (75 25)%
Input Rise and Fall Times (0 8V to 2 0V)
Crystal Input
All Other Inputs
5 ns max
10 ns max
Typical iJA
LFM
0
225
500
900
CW
54
45
38
34
DC Electrical Characteristics
over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C
Symbol
Parameter
Conditions
VCC e 4 5V to 5 5V
VCC T e 0 C to 70 C
Min Typ Max
VIH Minimum Input
High Level Voltage
45 20
55 20
VIL Maximum Input
Low LeveI Voltage
45 08
55 08
VOH
Minimum Output
High Level Voltage
IOH e b50 mA
45 44 44
55 54 54
VOL Maximum Output
Low Level Voltage
IOH e b30 mA
IOL e 50 mA
4 5 VCC b 0 6
5 5 VCC b 0 6
45
55
01
01
IOL e 30 mA
45
55
06
06
IOH High Level Output Current
IOL Low Level Output Current
IIN Leakage Current
VOH e VCC b 1 0V
VOL e 1 0V
VIN e 0 4V or 4 6V
4 5 50 110 170
4 5 50 110 170
4 5 b50
55
50 0
IOZL H Output Leakage Current
CIN Input Capacitance
VIN e GND
VOUT e VCC or GND
5 5 b5 0
45
50
a5 0
10 0
ICC
ICCT
Quiescent AnalogaDigital Current (No Load) VIN e VCC or GND
ICC per TTL Input
VIN e VCC b 2 1 or GND
55
55
3 50
25
Units
V
V
V
V
mA
mA
mA
mA
pF
mA
4

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CGS702 AC Electrical Characteristics
over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C
Symbol
Parameter
VCC e 4 5V to 5 5V
fIN e 25 MHz to 40 MHz
T e 0 C to 70 C
CL e Circuit 1 and 2
RL e Circuit 1 and 2
Min Typ Max
Units
Notes
tRISE
Output Rise
tFALL
Output Fall
tSKEW
Maximum
Edge-to-Edge
Output Skew
CLK4
CLK2
CLK1
0 8V to 2 6V
1 0V to VCC b 1 0V
1 0V to VCC b 1 0V
CLK4
CLK2
CLK1
2 6V to 0 8V
VCC b 1 0V to 1 0V
VCC b 1 0V to 1 0V
a to a Edges
a to a Edges
a to a Edges
CLK1 CLK1
CLK1 CLK4
CLK2 CLK4
2 0 ns (Note 1)
2 0 ns (Note 1)
500
1000 ps (Note 2)
1500
tLOCK
tCYCLE
Time to Lock the Output to the XTALIN Input
Output Duty Cycle
CLK1 Outputs
CLK2 Output
CLK4 Output
100 ms
49 51
49 51 % (Note 3)
35 65
JLT Output Jitter (Long Term)
JCC
Output Jitter
CLK1
(Cycle to Cycle) CLK2
300 ps (Notes 4 5)
b75
a75 ps (Notes 4 5 6)
g250
ps (Notes 4 5 7)
CLK4
g250
ps (Notes 4 5 7)
FMIN
Minimum XTALIN Frequency
15 MHz
FMAX
Maximum XTALIN Frequency
43 MHz
Note 1 tRISE and tFALL parameters are measured at the pin of the device
Note 2 Skew is measured at 50% of VCC for CLK1 and CLK2 While it is measured at 1 4V for CLK4
Note 3 Output duty cycle is measured at VDD 2 for CLK1 and CLK2 While it is measured at 1 4V for CLK4
Note 4 Jitter parameter is characterized and is guaranteed by design only It measures the uncertainty of either the positive or the negative edge over 1000 cycles
It is also measured at output levels of VCC 2 Refer to Figure 2 for further explanation
Note 5 The GNDA pins of the 702 must be as free of noise as possible for minimum jitter Separate analog ground plane is recommended for the PCB
Also the VCCA pin requires extra filtering to further reduce noise Ferrite beads for filtering and bypass capacitors are suggested for VCCA pin
Note 6 Cycle to Cycle Jitter is measured at VCC 2
Note 7 Cycle to Cycle Jitter for CLK2 and CLK4 is only for 25 C 5V measured VCC 2
TL F 12386 – 4
Circuit 1 Test Circuit for CLK1 and CLK2
TL F 12386 – 5
Circuit 2 Test Circuit for CLK4
5