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Data Sheet
Low Power Audio Codec
SSM2603
FEATURES
GENERAL DESCRIPTION
Stereo, 24-bit analog-to-digital and digital-to-analog converters
DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
Highly efficient headphone amplifier
Stereo line input and monaural microphone input
Low power
7 mW stereo playback (1.8 V/1.5 V supplies)
14 mW record and playback (1.8 V/1.5 V supplies)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital core: 1.5 V to 3.6 V
Digital I/O: 1.8 V to 3.6 V
256/384 oversampling rate in normal mode; 250/272 over-
sampling rate in USB mode
Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz
28-lead, 5 mm × 5 mm LFCSP (QFN) package
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The SSM2603 is a low power, high quality stereo audio codec
for portable digital audio applications with one set of stereo
programmable gain amplifier (PGA) line inputs and one
monaural microphone input. It features two 24-bit analog-to-
digital converter (ADC) channels and two 24-bit digital-to-
analog (DAC) converter channels.
The SSM2603 can operate as a master or a slave. It supports
various master clock frequencies, including 12 MHz or 24 MHz
for USB devices; standard 256 fS or 384 fS based rates, such as
12.288 MHz and 24.576 MHz; and many common audio sampling
rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24
kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.
The SSM2603 can operate at power supplies as low as 1.8 V for
the analog circuitry and as low as 1.5 V for the digital circuitry.
The maximum voltage supply is 3.6 V for all supplies.
The SSM2603 software-programmable stereo output options
provide the user with many application possibilities. Its volume
control functions provide a large range of gain control of the
audio signal.
The SSM2603 is specified over the industrial temperature range
of −40°C to +85°C. It is available in a 28-lead, 5 mm × 5 mm
lead frame chip scale package (LFCSP).
FUNCTIONAL BLOCK DIAGRAM
AVDD VMID AGND
DBVDD DGND DCVDD
HPVDD PGND
MICBIAS
–34.5dB TO +33dB,
1.5dB STEP
RLINEIN
MUX
MICIN
0dB/20dB BOOST
LLINEIN
–34.5dB TO +33dB,
1.5dB STEP
MUX
BYPASS
SIDETONE
–6dB TO –15dB/MUTE –3dB STEP
ADC
DIGITAL
PROCESSOR
ADC
DAC
DAC
–6dB TO –15dB/MUTE –3dB STEP
SIDETONE
BYPASS
SSM2603
–73dB TO +6dB,
1dB STEP
RHPOUT
ROUT
LOUT
LHPOUT
–73dB TO +6dB,
1dB STEP
CLK
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/ XTO CLKOUT
XTI
PBDAT RECDAT BCLK PBLRC RECLRC MUTE CSB SDIN SCLK
Figure 1.
Rev. C
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Technical Support
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SSM2603* Product Page Quick Links
Last Content Update: 08/30/2016
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SSM2603
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Filter Characteristics ....................................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Converter Filter Response........................................................... 9
Digital De-Emphasis .................................................................. 10
Theory of Operation ...................................................................... 11
Digital Core Clock...................................................................... 11
ADC and DAC............................................................................ 11
ADC High-Pass and DAC De-Emphasis Filters .................... 11
Hardware Mute Pin .................................................................... 11
Automatic Level Control (ALC)............................................... 12
Analog Interface ......................................................................... 13
REVISION HISTORY
6/13—Rev. B to Rev. C
Changes to Table 8............................................................................ 7
4/12—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Changes to Stereo Line and Monaural Microphone Inputs
Section and Figure 20..................................................................... 13
Changes to Table 10........................................................................ 19
Changes to Table 19 and Table 20 ................................................ 23
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
8/09—Rev. 0 to Rev. A
Changes to General Description Section and Figure 1 ............... 1
Changes to Specifications Section, Table 1 ................................... 3
Data Sheet
Digital Audio Interface .............................................................. 15
Software Control Interface........................................................ 17
Control Register Sequencing .................................................... 17
Typical Application Circuits ......................................................... 18
Register Map ................................................................................... 19
Register Map Details ...................................................................... 20
Left-Channel ADC Input Volume, Address 0x00.................. 20
Right-Channel ADC Input Volume, Address 0x01 ............... 21
Left-Channel DAC Volume, Address 0x02............................. 22
Right-Channel DAC Volume, Address 0x03 .......................... 22
Analog Audio Path, Address 0x04 ........................................... 23
Digital Audio Path, Address 0x05 ............................................ 23
Power Management, Address 0x06.......................................... 24
Digital Audio I/F, Address 0x07 ............................................... 25
Sampling Rate, Address 0x08.................................................... 25
Active, Address 0x09.................................................................. 28
Software Reset, Address 0x0F................................................... 28
ALC Control 1, Address 0x10................................................... 29
ALC Control 2, Address 0x11................................................... 29
Noise Gate, Address 0x12.......................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Changes to Master Clock Tolerance, Frequency Range
Parameter, Table 2 .............................................................................4
Added Endnote 1, Table 2 ................................................................4
Changes to Table 6.............................................................................6
Changes to Figure 6 and Table 9......................................................8
Changes to Digital Core Clock Section ....................................... 11
Changes to Digital Audio Data Sampling Rate Section ............ 15
Changes to Figure 31...................................................................... 18
Added Control Register Sequencing Section.............................. 17
Change to Table 10 ......................................................................... 19
Changes to Table 15, Table 16, Table 17, and Table 18 .............. 22
Changes to Table 37 ....................................................................... 29
Added Exposed Pad Notation to Outline Dimensions ............. 31
2/08—Revision 0: Initial Version
Rev. C | Page 2 of 32

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Data Sheet
SSM2603
SPECIFICATIONS
TA = 25°C, AVDD = DVDD = 3.3 V, HPVDD = 3.3 V, 1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted.
Table 1.
Parameter
RECOMMENDED OPERATING CONDITIONS
Analog Voltage Supply (AVDD)
Digital Core Power Supply
Digital I/O Supply
Ground (AGND, PGND, DGND)
POWER CONSUMPTION
Power-Up
Stereo Record (1.5 V and 1.8 V)
Stereo Record (3.3 V)
Stereo Playback (1.5 V and 1.8 V)
Stereo Playback (3.3 V)
Power-Down
LINE INPUT
Input Signal Level (0 dB)
Input Impedance
Input Capacitance
Signal-to-Noise Ratio (A-Weighted)
THD + N
Channel Separation
Programmable Gain
Gain Step
Mute Attenuation
MICROPHONE INPUT
Input Signal Level
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion
Power Supply Rejection Ratio
Mute Attenuation
Input Resistance
Input Capacitance
MICROPHONE BIAS
Bias Voltage
Bias Current Source
Noise in the Signal Bandwidth
LINE OUTPUT1
Full-Scale Output
Signal-to-Noise Ratio (A-Weighted)
THD + N
Power Supply Rejection Ratio
Channel Separation
Min Typ
1.8 3.3
1.5 3.3
1.8 3.3
0
Max Unit
3.6 V
3.6 V
3.6
V
Conditions
7
22
7
22
40
70
−34.5
1 × AVDD/3.3
200
10
480
10
90
84
−80
−75
80
0
1.5
−80
+33
1 × AVDD/3.3
85
−70
50
80
10
10
0.75 × AVDD
40
3
1 × AVDD/3.3
85 100
94
−80 −70
−75
50
80
mW
mW
mW
mW
μW
V rms
pF
dB
dB
dB
dB
dB
dB
dB
dB
PGA gain = 0 dB
PGA gain = +33 dB
PGA gain = −34.5 dB
PGA gain = 0 dB, AVDD = 3.3 V
PGA gain = 0 dB, AVDD = 1.8 V
−1 dBFS input, AVDD = 3.3 V
−1 dBFS input, AVDD = 1.8 V
V rms
dB
dB
dB
dB
pF
Microphone gain = 0 dB (REXT = 40 kΩ)
−1 dBFS input, 0 dB gain
V
mA
nV/√Hz
20 Hz to 20 kHz
V rms
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
Rev. C | Page 3 of 32

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SSM2603
Parameter
HEADPHONE OUTPUT
Full-Scale Output Voltage
Maximum Output Power
Signal-to-Noise Ratio (A-Weighted)
THD + N
Power Supply Rejection Ratio
Mute Attenuation
LINE INPUT TO LINE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
THD + N
Power Supply Rejection
MICROPHONE INPUT TO HEADPHONE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
Power Supply Rejection Ratio
Programmable Attenuation
Gain Step
Mute Attenuation
Min Typ
1 × AVDD/3.3
30
60
85 96
90
−65
−60
50
80
1 × AVDD/3.3
92
86
−80
−80
50
1 × AVDD/3.3
94
88
50
6
3
80
1 The line output is tested by sending a −1 dBFS input from the DAC to the line output.
Max
15
Unit
V rms
mW
mW
dB
dB
dB
dB
dB
dB
V rms
dB
dB
dB
dB
dB
V rms
dB
dB
dB
dB
dB
dB
Conditions
RL = 32 Ω
RL = 16 Ω
AVDD = 3.3 V
AVDD = 1.8 V
POUT = 10 mW
POUT = 20 mW
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
DIGITAL FILTER CHARACTERISTICS
Table 2.
Parameter
ADC FILTER
Pass Band
Min
0
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
High-Pass Filter Corner Frequency
0.555 fS
−61
DAC FILTER
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
MASTER CLOCK TOLERANCE1
Frequency Range
Jitter Tolerance
1 CLKDIV2 bit (Register R8, Bit D6) is set to 0.
0
0.555 fS
−61
8.0
Typ
0.5 fS
3.7
10.4
21.6
0.5 fS
50
Max
0.445 fS
±0.04
0.445 fS
±0.04
18.5
Unit
Hz
Hz
dB
Hz
dB
Hz
Hz
Hz
Hz
Hz
dB
Hz
dB
MHz
ps
Conditions
±0.04 dB
−6 dB
f > 0.567 fS
−3 dB
−0.5 dB
−0.1 dB
±0.04 dB
−6 dB
f > 0.565 fS
Data Sheet
Rev. C | Page 4 of 32