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Data Sheet
5 kV, 7-Channel,
SPIsolator Digital Isolators for SPI
ADuM4151/ADuM4152/ADuM4153
FEATURES
Supports up to 17 MHz SPI clock speed
4 high speed, low propagation delay, SPI signal isolation
channels
Three 250 kbps data channels
20-lead SOIC_IC package with 8.3 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL recognition per UL 1577
5000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Maximum working insulation voltage (VIORM): 849 V peak
APPLICATIONS
Industrial programmable logic controllers (PLCs)
Sensor isolation
GENERAL DESCRIPTION
The ADuM4151/ADuM4152/ADuM41531 are 7-channel,
SPIsolator™ digital isolators optimized for isolated serial peripheral
interfaces (SPIs). Based on the Analog Devices, Inc., iCoupler®
chip scale transformer technology, the low propagation delay in
the CLK, MO/SI, MI/SO, and SS SPI bus signals supports SPI
clock rates of up to 17 MHz. These channels operate with 14 ns
propagation delay and 1 ns jitter to optimize timing for SPI.
The ADuM4151/ADuM4152/ADuM4153 isolators also provide
three additional independent low data rate isolation channels in
three different channel direction combinations. Data in the slow
channels is sampled and serialized for a 250 kbps data rate with
up to 2.5 µs of jitter in the low speed channels.
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM4151
ENCODE
ENCODE
DECODE
ENCODE
VIA 7
VIB 8
VOC 9
CONTROL
BLOCK
GND1 10
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VOA
13 VOB
12 VIC
11 GND2
Figure 1. ADuM4151 Functional Block Diagram
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM4152
ENCODE
ENCODE
DECODE
ENCODE
VIA 7
VOB 8
VOC 9
CONTROL
BLOCK
GND1 10
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VOA
13 VIB
12 VIC
11 GND2
Figure 2. ADuM4152 Functional Block Diagram
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM4153
ENCODE
ENCODE
DECODE
ENCODE
VOA 7
VOB 8
VOC 9
CONTROL
BLOCK
GND1 10
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VIA
13 VIB
12 VIC
11 GND2
Figure 3. ADuM4153 Functional Block Diagram
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. A
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ADuM4151/ADuM4152/ADuM4153
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7
Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 9
Package Characteristics ............................................................. 10
Regulatory Information............................................................. 11
Insulation and Safety Related Specifications .......................... 11
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics.......................................................... 12
REVISION HISTORY
3/15—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Table 2............................................................................ 3
Changes to Table 5............................................................................ 5
Changes to Table 8............................................................................ 7
Changes to Table 11.......................................................................... 9
Changes to Table 14........................................................................ 11
Changes to Table 16........................................................................ 12
Changes to High Speed Channels Section .................................. 18
10/14—Revision 0: Initial Version
Data Sheet
Recommended Operating Conditions .................................... 12
Absolute Maximum Ratings ......................................................... 13
ESD Caution................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 17
Applications Information .............................................................. 18
Introduction................................................................................ 18
Printed Circuit Board (PCB) Layout ....................................... 19
Propagation Delay Related Parameters ................................... 19
DC Correctness and Magnetic Field Immunity..................... 19
Power Consumption .................................................................. 20
Insulation Lifetime ..................................................................... 20
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
Rev. A | Page 2 of 22

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Data Sheet
ADuM4151/ADuM4152/ADuM4153
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V. Minimum and maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 1. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time2
Jitter, High Speed
VIA, VIB, VIC
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx3 Minimum Input Skew4
Symbol
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JHS
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW3
A Grade
Min Typ Max
100
1
1
2
25
3
3
21
100
1.5
1
2
25
3
250
0.1 2.6
4
2.5
10
B Grade
Min Typ Max
12
12.5
1
17
34
14
2
2
21
12.5
10
1
34
25
3
250
0.1 2.6
4
2.5
10
Unit
MHz
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
kbps
µs
µs
µs
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 VIx = VIA, VIB, or VIC.
4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Table 2. Supply Current
Device Number
ADuM4151
ADuM4152
ADuM4153
Symbol
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
1 MHz, A Grade
17 MHz, B Grade
Min Typ Max Min Typ Max Unit Test Conditions/Comments
4.0 8.5
6.0 11
14.0 22
13.5 23
mA CL = 0 pF, low speed channels
mA CL = 0 pF, low speed channels
4.8 8.5
6.5 10.5
14.0 21.5
14.0 22.5
mA
mA
CL = 0 pF, low speed channels
CL = 0 pF, low speed channels
4.0 8.5
14.0 22
mA CL = 0 pF, low speed channels
6.0 10.5
13.3 21
mA CL = 0 pF, low speed channels
Rev. A | Page 3 of 22

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ADuM4151/ADuM4152/ADuM4153
Data Sheet
Table 3. For All Models1, 2, 3
Parameter
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB, VIC
Logic High Input Threshold
Logic Low Input Threshold
Input Hysteresis
Input Current per Channel
SCLK, SSS, MI, SI, VOA, VOB, VOC
Logic High Output Voltages
Logic Low Output Voltages
VDD1, VDD2 Undervoltage Lockout
Supply Current per High Speed Channel
Dynamic Input Supply Current
Dynamic Output Supply Current
Supply Current for All Low Speed Channels
Quiescent Side 1 Current
Quiescent Side 2 Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity4
Symbol
VIH
VIL
VIHYST
II
VOH
VOL
UVLO
IDDI(D)
IDDO(D)
IDD1(Q)
IDD2Q)
tR/tF
|CM|
Min
0.7 × VDDx
−1
VDDx − 0.1
VDDx − 0.4
25
Typ
500
+0.01
5.0
4.8
0.0
0.2
2.6
0.080
0.046
4.3
6.1
2.5
35
Max
0.3 × VDDx
+1
0.1
0.4
Unit
V
V
mV
µA
V
V
V
V
V
mA/Mbps
mA/Mbps
mA
mA
ns
kV/µs
Test Conditions/Comments
0 V ≤ VINPUT ≤ VDDx
IOUTPUT = −20 µA, VINPUT = VIH
IOUTPUT = −4 mA, VINPUT = VIH
IOUTPUT = 20 µA, VINPUT = VIL
IOUTPUT = 4 mA, VINPUT = VIL
10% to 90%
VINPUT = VDDx, VCM = 1000 V,
transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, or VIC pins.
3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, or VOC pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 4 of 22

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Data Sheet
ADuM4151/ADuM4152/ADuM4153
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted.
Table 4. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time2
Jitter, Low Speed
VIA, VIB, VIC
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx3 Minimum Input Skew4
Symbol
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JLS
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW3
A Grade
Min Typ Max
100
1
1
2
30
3
4
2
30
100
3
1.5
2.5
250
0.1 2.6
4
2.5
10
B Grade
Min Typ Max
12.5
1
12.5
34
20
3
2
12.5
10
2.5
34
30
3
250
0.1 2.6
4
2.5
10
Unit
MHz
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
kbps
µs
µs
µs
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 VIx = VIA, VIB, or VIC.
4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Table 5. Supply Current
Device Number
ADuM4151
ADuM4152
ADuM4153
Symbol
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
1 MHz, A Grade/B Grade
Min Typ Max
3.8 7
5.1 8
3.7 6.5
5.2 8
3.7 6.5
5.2 9
17 MHz, B Grade
Min Typ Max Unit Test Conditions/Comments
10.5 18
mA CL = 0 pF, low speed channels
9.0 17
mA CL = 0 pF, low speed channels
11.7 18
mA CL = 0 pF, low speed channels
10.0 16
mA CL = 0 pF, low speed channels
11.7 18
mA CL = 0 pF, low speed channels
10.0 15
mA CL = 0 pF, low speed channels
Rev. A | Page 5 of 22