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DATASHEET
ISL70003ASEH
Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator
FN8746
Rev: 4.00
Sep 13, 2018
The ISL70003ASEH is an improved version of the
ISL70003SEH regulator with both tighter load regulation
(<0.3% typical) and a higher output current rating of 9A.
Operating over an input voltage range of 3.0V to 13.2V with
integrated low rDS(ON) MOSFETs makes this monolithic
solution highly efficient. Also, a tightly regulated output
voltage is possible, which is externally adjustable from 0.6V to
~90% of the input voltage. Continuous output load current
capability is 9A for TJ +125°C and 6A for TJ +150°C.
The ISL70003ASEH uses voltage mode control architecture
with feed-forward and switches at a selectable frequency of
500kHz or 300kHz. Loop compensation is externally
adjustable to allow for an optimum balance between stability
and output dynamic performance.
The device features two logic-level disable inputs that can be
used to inhibit pulses on the phase (LXx) pins to maximize
efficiency based on the load current. The ISL70003ASEH also
supports DDR applications and contains a buffer amplifier for
generating the VREF voltage.
High integration, best-in-class radiation performance and a
feature-filled design make the ISL70003ASEH an ideal choice
to power many of today’s small form-factor applications.
Applications
• FPGA, CPLD, DSP, CPU core, and I/O supply voltages
• DDR memory supply voltages
• Low-voltage, high-density distributed power systems
Related Literature
For a full list of related documents, visit our website
ISL70003ASEH product page
Features
• Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer
• ±1% reference voltage over line, temperature, and radiation
• Integrated MOSFETs 31mΩPFET/21mΩ NFET
- 95% peak efficiency
• Externally adjustable loop compensation
• Supports DDR applications (VTT tracks VDDQ/2)
- Buffer amplifier for generating VREF voltage
- 3A current sinking capability
• Grounded lid eliminates charge build up
• IMON pin for output current monitoring
• Adjustable analog soft-start
• Diode emulation for increased efficiency at light loads
• 500kHz or 300kHz operating frequency
• Monotonic start-up into prebiased load
• Full military temperature range operation
- TA = -55°C to +125°C
- TJ = -55°C to +150°C
• Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Limit established by characterization.
• SEE hardness
- SEB and SEL LETTH . . . . . . . . . . . . . . . . 86.4MeV•cm2/mg
- SET at LET 86.4MeV•cm2/mg . . . . . . . . . . . .<±3% ΔVOUT
- SEFI LETTH . . . . . . . . . . . . . . . . . . . . . . . . . 60MeV•cm2/mg
• Electrically screened to DLA SMD 5962-14203
12V INTERMEDIATE BUS
ISL70003ASEH
5V BUS
ISL70003ASEH
ISL75051ASEH
1.5V CORE
1.8V AUX
ISL75051ASEH
3.3V I/O
FIGURE 1. POWER DISTRIBUTION SOLUTION FOR RAD HARD LOW
POWER FPGAs
0.3
0.2 -55°C
0.1
+25°C
+125°C
0.0
-0.1
+85°C
-0.2
-0.30 1 2 3 4 5 6 7 8 9
LOAD CURRENT (A)
FIGURE 2. TYPICAL LOAD REGULATION, VIN = 12V, VOUT = 3.3V,
fSW = 500kHz
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ISL70003ASEH
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .10
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Recommended Operating Conditions . . . . . . . . . . . . . . . . .10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .13
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . 21
Undervoltage and Overvoltage Monitor. . . . . . . . . . . . . . . . . . 21
Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Load Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Voltage Feed-Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . 23
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setting the Overcurrent Protection Level . . . . . . . . . . . . . . . . 23
Disabling the Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IMON Current-Sense Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DDR Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DDR Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operational Envelope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High Current Protection Clamp . . . . . . . . . . . . . . . . . . . . . . 26
Derating Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . 27
General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Output Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Feedback Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Modulator Break Frequency Equations . . . . . . . . . . . . . . . . . 29
Compensation Break Frequency Equations . . . . . . . . . . . . . 29
PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PCB Plane Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PCB Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LX Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Lead Strain Relief . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Heatsink Mounting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . 30
Heatsink Electrical Potential . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Heatsink Mounting Materials . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Weight of Packaged Device . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Lid Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Die Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Die Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interface Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Metallization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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ISL70003ASEH
Functional Block Diagram
POR_VIN
RT/CT
SS_CAP
NI
FB
VERR
PGOOD
REF
BUFIN-
BUFIN+
BUFOUT
SYNC
FSEL
DE
POR AND ON/OFF
CONTROL
RAMP
SOFT-
START
EA
COMP
PWM
CONTROL
LOGIC
LINEAR
REGULATORS
CURRENT
SENSE
GATE
DRIVE
PWM
REFERENCE
0.6V
VOUT
MONITOR
BUF
DDR VREF
BUFFER AMP
OVERCURRENT
ADJUST
PGNDx
FIGURE 3. BLOCK DIAGRAM
AVDD
DVDD
SEL1
SEL2
IMON
PVINx
LXx
SGND
PGNDx
OCSETA
OCSETB
DGND
AGND
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ISL70003ASEH
Ordering Information
ORDERING SMD
NUMBER (Note 1)
PART NUMBER
(Note 2)
TEMPERATURE
RANGE (°C)
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
5962R1420302VYC
ISL70003ASEHVFE
-55 to +125
64 Ld CQFP with Heatsink
R64.C
5962R1420302V9A
ISL70003ASEHVX
-55 to +125
Die
N/A
ISL70003ASEHFE/PROTO (Note 3)
-55 to +125
64 Ld CQFP with Heatsink
R64.C
N/A
ISL70003ASEHX/SAMPLE (Note 3)
-55 to +125
Die
N/A
ISL70003ASEHEV1Z (Note 4)
Full Featured Evaluation Board
N/A
ISL70003ASEHEV2Z (Note 4)
Small Form Factor Evaluation Board
NOTES:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be
used when ordering.
2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for
engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across temperature specified in the DLA SMD and
are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the
DLA SMD at +25°C only. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types
do not come with a Certificate of Conformance because they are not DLA qualified devices.
4. Evaluation board uses the /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity.
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ISL70003ASEH
Pin Configuration
BOTTOM SIDE DETAIL
FOR PIN 1 LOCATION
64 LD CQFP
TOP VIEW
1 (NI) NI
FB
VERR
POR_VIN
VREFA
AVDD
AGND
DGND
VREF_OUTS
DVDD
VREFD
ENABLE
RT/CT
FSEL
SYNC
SS_CAP
1 64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
2 47
3 46
4 45
5 44
6 (Note 5)
43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14
HEATSINK OUTLINE *
35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LX3
PGND3
PGND4
LX4
PVIN4
PVIN5
LX5
PGND5
PGND6
LX6
PVIN6
PVIN7
LX7
PGND7
PGND8
LX8
NOTE:
5. The ESD triangular mark is indicative of Pin #1 location. It is part of the device marking and is
placed on the lid in the quadrant where Pin #1 is located.
* Indicates heatsink package R64.C
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
PIN NAME
NI
FB
VERR
POR_VIN
VREFA
AVDD
ESD CIRCUIT
DESCRIPTION
1 The noninverting input to the internal error amplifier. Connect this pin to the REF pin for typical
applications. For DDR memory power applications, connect NI to the BUFOUT pin.
1 The inverting input to the internal error amplifier. Connect an external Type III compensation network
between this pin and the VERR pin. The connection between the FB resistor divider and the output
inductor should be a Kelvin connection to optimize performance.
1 The output of the internal error amplifier. Connect an external compensation network between this pin
and the FB pin.
1 The power-on reset input to the IC. This is a comparator-type input with a rising threshold of 0.6V and
programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a
10nF ceramic capacitor to mitigate SEE.
3 The output of an internal linear regulator and is the bias supply input to the internal analog control
circuitry. The output voltage is ~PVIN when PVIN <5V and is 5V when PVIN 5V. Do not use this pin for
external circuitry. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible
to the IC.
5 This pin provides the supply for the internal linear regulator of the ISL70003ASEH. The supply to AVDD
should be locally bypassed using a ceramic capacitor. Tie AVDD to the PVINx pins.
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