Manual Reset Input with an internal pull-up. Active low. MR low forces the reset
output RESET low. Required minimum MR pulse width is 150ns. RESET is held low
for duration of the reset timer.
Power supply. Operating voltage range is 3.15V to 3.6V. VDD level is monitored
internally by a dedicated comparator circuit, which employs an internal bandgap
voltage reference nominally equal to 1.25V. Every time VDD falls below the threshold
voltage, nominally 3.08V, RESET and WDO outputs are forced low. (See WDO and
RESET descriptions.) (Figure 4.)
Ground. This pin should be tied to ground and establishes the reference for voltage
Threshold detector input. Voltage on this input is fed directly to an internal
comparator where it is compared to the voltage reference of 0.6V. It can be used for
detection of low battery or power failure of voltage supplies other than VDD. When
voltage at PFI input drops below its threshold value of 0.6V, PFO output is forced low,
otherwise, stays high.
Threshold detector output. Active low push-pull output driver. It responds directly
to PFI input. If PFI voltage is below the bandgap reference voltage, PFO is low. If PFI
is above the reference voltage, PFO output is high.
Watchdog timer input pin. This pin is typically used to monitor microprocessor
activity. It can assume three states: low, high and float. If WDI is floating or connected
to a high impedance three state buffer, the watchdog timer is not active, and the
corresponding watchdog output WDO is high. Watchdog timer is also not active any
time RESET is low. Providing that RESET is not asserted, any change of state at WDI
that is longer than 100ns will start the timer, or restart it, if the timer is already running
(Figure 3.). If there is no activity within the timeout period, nominally 1.6s, the timer
will stop running and WDO output will go low (Figure 3).
Reset output. Active low push-pull output driver. This pin is pulled up with a resistor
consistant with the sink and voltage current as specified in the electrical characteristics
table. This output responds to both: VDD monitoring circuits and the manual reset
On power up, RESET is guaranteed to be logic low for all VDD values from 1.2V up
to the reset threshold, nominally 3.08V. Once this threshold is reached, an internal
RESET timer is activated. During the countdown RESET output is kept low. It is
raised high upon completion of countdown, typically after 200ms. If a brown out
condition occurs during the reset timer countdown, the reset timer would be reset and
another countdown would start after VDD levels were restored above the reset
threshold. On power down, when VDD falls below the threshold voltage, RESET goes
low and is guaranteed to stay low until VDD drops below 1.2V.
If MR is asserted low, RESET is forced low and the reset timer is kept reset. When
MR is released high, the timer is activated and RESET is kept low until completion
of the reset timeout, when it is raised high.