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DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
FINAL
General Description
AES-128 bit encryption Processor
The DA14581 integrated circuit is an optimized version
of the DA14580, offering a reduced boot time and sup-
porting up to 8 connections. It has a fully integrated
radio transceiver and baseband processor for Blue-
tooth® low energy. It can be used as a standalone
application processor or as a data pump in hosted sys-
tems.
Memories
32 kB One-Time-Programmable (OTP) memory
42 kB System SRAM
84 kB ROM
8 kB Retention SRAM
Power management
Integrated Buck/Boost DC-DC converter
P0, P1 and P2 ports with 3.3 V tolerance
The DA14581 supports a flexible memory architecture
Easy decoupling of only 4 supply pins
for storing Bluetooth profiles and custom application
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
code, which can be updated over the air (OTA). The
battery cells
qualified Bluetooth low energy protocol stack and the
10-bit ADC for battery voltage measurement
HCI ready software are stored in a dedicated ROM. All
software runs on the ARM® Cortex®-M0 processor via
Digital controlled oscillators
16 MHz crystal (±20 ppm max) and RC oscillator
a simple scheduler.
32 kHz crystal (±50 ppm, ±500 ppm max) and
The Bluetooth low energy firmware includes the
L2CAP service layer protocols, Security Manager
(SM), Attribute Protocol (ATT), the Generic Attribute
Profile (GATT) and the Generic Access Profile (GAP).
All profiles published by the Bluetooth SIG as well as
custom profiles are supported.
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
Gen. purpose I/Os: 14 (WLCSP34), 24 (QFN40)
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
I2C bus at 100 kHz, 400 kHz
The transceiver interfaces directly to the antenna and
3-axes capable Quadrature Decoder
is fully compliant with the Bluetooth 4.2 standard.
Analog interfaces
The DA14581 has dedicated hardware for the Link
Layer implementation of Bluetooth low energy and
interface controllers for enhanced connectivity capabili-
ties.
4-channel 10-bit ADC
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
Single wire antenna: no RF matching or RX/TX
switching required
Features
Supply current at VBAT3V:
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
Complies with Bluetooth V4.2, ETSI EN 300 328 and
0 dBm transmit output power
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
-20 dBm output power in “Near Field Mode”
(US) and ARIB STD-T66 (Japan)
-93 dBm receiver sensitivity
Supports up to 8 Bluetooth low energy connections
Packages:
Fast cold boot in less than 30 ms
Ultra-Thin WLCSP 34 pins, 2.436 mm x 2.436 mm
Processing power
x 0.334 mm
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
WLCSP 34 pins, 2.436 mm x 2.436 mm
face x 0.511 mm
Dedicated Link Layer Processor
QFN 40 pins, 5 mm x 5 mm
________________________________________________________________________________________________
System Diagram
Datasheet
CFR0011-120-01
Revision 3.2
1 of 153
17-Jan-2017
© 2014 Dialog Semiconductor

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DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 7
4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 ARM CORTEXM0 CPU . . . . . . . . . . . . . . . . . . 8
4.2 BLUETOOTH LOW ENERGY . . . . . . . . . . . . . . 8
4.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . . 9
4.2.3 SmartSnippets  
4.3 MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . 10
4.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . .11
4.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.2 SPI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.3 I2C Interface . . . . . . . . . . . . . . . . . . . . . .11
4.6.4 General Purpose ADC . . . . . . . . . . . . . . 12
4.6.5 Quadrature Decoder . . . . . . . . . . . . . . . 12
4.6.6 Keyboard Controller . . . . . . . . . . . . . . . . 12
4.6.7 Input/Output Ports . . . . . . . . . . . . . . . . . 12
4.7 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.7.1 General Purpose Timers . . . . . . . . . . . . 12
4.7.2 Wake-Up Timer . . . . . . . . . . . . . . . . . . . 13
4.7.3 Watchdog Timer. . . . . . . . . . . . . . . . . . . 13
4.8 CLOCK/RESET . . . . . . . . . . . . . . . . . . . . . . . . 13
4.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 14
5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . 149
7.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 149
7.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . . 149
7.3 SOLDERING INFORMATION . . . . . . . . . . . . 149
7.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 150
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.2
2 of 153
FINAL
17-Jan-2017
© 2014 Dialog Semiconductor

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DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
1 Block Diagram
FINAL
24 April 2012
ARM Cortex M0
CORE
SWD (JTAG)
System/
Exchange
RAM
42 kB
Ret. RAM
2 kB
Ret. RAM2
3 kB
Ret. RAM3
2 kB
Ret. RAM4
1 kB
OTP
32 kB
DMA
OTPC
ROM
84 kB
Datasheet
CFR0011-120-01
XTAL
32.768 kHz
XTAL
16 MHz
BLE Core
DCDC
(BUCK/BOOST)
LDO
SYS
LDO
RET
LSLSDYLDYORSDOSFO
AES-128
LINK LAYER
HARDWARE
RC RC
16 MHz 32 kHz
RCX
POReset
Radio
Transceiver
SW TIMER
Timer 0
1xPWM
Timer 2
3xPWM
GPIO MULTIPLEXING
Figure 1: DA14581 Block Diagram
Revision 3.2
3 of 153
17-Jan-2017
© 2014 Dialog Semiconductor

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DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
FINAL
2 Pinout
The DA14581 comes in three packages:
• A Wafer Level Chip Scale Package (WLCSP) with
34 balls (normal thickness and ultra-thin)
• A Quad Flat Package No Leads (QFN) with 40 pins
The actual pin/ball assignment is depicted in the follow-
ing figures:
123456
A
B
C
D
E
F
DA14581 (Top View)
Figure 2: WLCSP Ball Assignment
P0_0
P0_1
P0_2
P0_3
NC
P0_4
P0_5
P2_1
P0_6
P0_7
1
2
3
4
5
6
7
8
9
10
DA14581
(Top View)
30 XTAL16Mm
29 XTAL16Mp
28 P1_3
27 P1_2
26 SW_CLK
25 SWDIO
24 P1_1
23 VBAT1V
22 P1_0
21 SWITCH
Pin 0: GND
plane
Figure 3: QFN40 Pin Assignment
Datasheet
CFR0011-120-01
Revision 3.2
4 of 153
17-Jan-2017
© 2014 Dialog Semiconductor

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DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
FINAL
Table 1: Pin Description
Pin Name
Type
General Purpose I/Os
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P1_0
P1_1
P1_2
P1_3
P1_4/SWCLK
P1_5/SW_DIO
DIO
DIO
DIO
DIO
DIO
DIO
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P2_8
P2_9
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P3_0 to P3_7
DIO
Debug interface
SWDIO/P1_5
DIO
Drive
(mA)
4.8
4.8
4.8
4.8
4.8
SW_CLK/
P1_4
DIO
Clocks
XTAL16Mp
AI
XTAL16Mm
AO
XTAL32kp
AI
XTAL32km
AO
Quadrature Decoder
QD_CHA_X
DI
QD_CHB_X
DI
QD_CHA_Y
DI
QD_CHB_Y
DI
QD_CHA_Z
DI
QD_CHB_Z
DI
SPI Bus Interface
SPI_CLK
DO
SPI_DI
DI
SPI_DO
DO
Datasheet
CFR0011-120-01
4.8
Reset
State
Description
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
This signal is the JTAG clock by default
This signal is the JTAG data I/O by default
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
NOTE: This port is only available on the QFN40 package.
Not supported.
I-PU
I-PD
INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and
control communication. Can also be used as a GPIO
INPUT JTAG clock signal. Can also be used as a GPIO
INPUT. Crystal input for the 16 MHz XTAL
OUTPUT. Crystal output for the 16 MHz XTAL
INPUT. Crystal input for the 32.768 kHz XTAL
OUTPUT. Crystal output for the 32.768 kHz XTAL
INPUT. Channel A for the X axis. Mapped on Px ports
INPUT. Channel B for the X axis. Mapped on Px ports
INPUT. Channel A for the Y axis. Mapped on Px ports
INPUT. Channel B for the Y axis. Mapped on Px ports
INPUT. Channel A for the Z axis. Mapped on Px ports
INPUT. Channel B for the Z axis. Mapped on Px ports
INPUT/OUTPUT. SPI Clock. Mapped on Px ports
INPUT. SPI Data input. Mapped on Px ports
OUTPUT. SPI Data output. Mapped on Px ports
Revision 3.2
5 of 153
17-Jan-2017
© 2014 Dialog Semiconductor