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Quad Digital Potentiometers
(DP) with 64 Taps and 2-wire Interface
DP7409
FEATURES
Four linear taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kŸ, 10kŸ, 50kŸ or
100kŸ
2-wire interface (I2C like)
Low wiper resistance, typically 80Ÿ
Four non-volatile wiper settings for each
potentiometer
Recall of saved wiper settings at power-up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Write protection for data register
For Ordering Information details, see page 15.
PIN CONFIGURATION
TSSOP (Y)
SOIC (W)
SDA 1
A1 2
RL1 3
RH1 4
RW1 5
GND 6
NC 7
RW2 8
RH2 9
RL2 10
SCL 11
A3 12
24 WP
23 A2
22 RW0
21 RH0
20 RL0
19 VCC
18 NC
17 RL3
16 RH3
15 RW3
14 A0
13 NC
VCC 1
RL0 2
RH0 3
RW0 4
A2 5
WP 6
SDA 7
A1 8
RL1 9
RH1 10
RW1 11
GND 12
24 NC
23 RL3
22 RH3
21 RW3
20 A0
19 NC
18 A3
17 SCL
16 RL2
15 RH2
14 RW2
13 NC
DESCRIPTION
The DP7409 is four Digital Potentiometers
(DP) integrated with control logic and 16 bytes
of NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DP.
Associated with each wiper control register are four
6-bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data
registers is via a 2-wire serial bus (I2C-like). On
power-up, the contents of the first data register (DR0)
for each of the four potentiometers is automatically
loaded into its respective wiper control register
(WCR).
The Write Protection (¯W¯P¯) pin protects against
inadvertent programming of the data register.
The DP7409 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
FUNCTIONAL DIAGRAM
SCL
SDA
WP
A0
A1
A2
A3
RH0
RH1
RH2
RH3
2-WIRE BUS
INTERFACE
WIPER CONTROL
REGISTERS
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
RW0
RW1
RW2
RW3
RL0 RL1 RL2
RL3
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2010 Rev. K

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DP7409
PIN DESCRIPTIONS
Pin# Pin#
(TSSOP) (SOIC)
19 1
20 2
21 3
22 4
23 5
24 6
17
28
39
4 10
5 11
6 12
7 13
8 14
9 15
10 16
11 17
12 18
13 19
14 20
15 21
16 22
17 23
18 24
Name
VCC
RL0
RH0
RW0
A2
¯W¯P¯
SDA
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
SCL
A3
NC
A0
RW3
RH3
RL3
NC
Function
Supply Voltage
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for
Potentiometer 0
Device Address
Write Protection
Serial Data Input/Output
Device Address
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
Wiper Terminal for
Potentiometer 1
Ground
No Connect
Wiper Terminal for
Potentiometer 2
High Reference Terminal
for Potentiometer 2
Low Reference Terminal
for Potentiometer 2
Bus Serial Clock
Device Address
No Connect
Device Address, LSB
Wiper Terminal for
Potentiometer 3
High Reference Terminal
for Potentiometer 3
Low Reference Terminal
for Potentiometer 3
No Connect
SCL: Serial Clock
The DP7409 serial clock input pin is used to clock all
data transfers into or out of the device.
SDA: Serial Data
The DP7409 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin is
an open drain output and can be wire-Ored with the
other open drain or open collector outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of sixteen devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in order
to initiate communication with the DP7409.
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
RW: Wiper
The four RW pins are equivalent to the wiper terminal of
a mechanical potentiometer.
¯W¯P¯: Write Protect Input
The ¯W¯P¯ pin when tied low prevents non-volatile writes
to the data registers (change of wiper control register is
allowed) and when tied high or left floating normal
read/write operations are allowed. See Write Protection
on page 7 for more details.
DEVICE OPERATION
The DP7409 is four resistor arrays integrated with 2-wire serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and
at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch.
Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile
memory data registers via the 2-wire bus. Additional instructions allows data to be transferred between the wiper
control registers and each respective potentiometer's non-volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement" mode.
Doc. No. MD-2010 Rev. K
2 © NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice

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ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to VSS(1) (2)
VCC with Respect to Ground
Package Power Dissipation Capability (TA = 25ºC)
Lead Soldering Temperature (10sec)
Wiper Current
RECOMMENDED OPERATING CONDITIONS
Parameters
VCC
Industrial Temperature
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
RPOT
RPOT
RPOT
RPOT
IW
RW
RW
VTERM
TCRPOT
TCRATIO
CH/CL/CW
fc
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance
Tolerance
RPOT Matching
Power Rating
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any RH or RL Pin
Resolution
Absolute Linearity (5)
Relative Linearity (6)
Temperature Coefficient of RPOT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Test Conditions
25°C, each pot
IW = ±3mA @ VCC = 3V
IW = ±3mA @ VCC = 5V
VSS = 0V
RW(n)(actual) - R(n)(expected)(8)
RW(n+1) - [RW(n) + LSB](8)
(4)
(4)
(4)
RPOT = 50kŸ (4)
DP7409
Ratings
-55 to +125
-65 to +150
-2.0 to +VCC + 2.0
-2.0 to +7.0
1.0
300
±12
Units
ºC
°C
V
V
W
ºC
mA
Ratings
+2.5 to +6
-40 to +85
Units
V
°C
Min Typ Max Units
100 kŸ
50 kŸ
10 kŸ
2.5 kŸ
±20 %
GND
80
1.6
±300
10/10/25
0.4
1
50
±6
300
150
VCC
±1
±0.2
20
%
mW
mA
Ÿ
Ÿ
V
%
LSB (7)
LSB (7)
ppm/ºC
ppm/ºC
pF
MHz
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-
meter. It is a measure of the error in step size.
(7) LSB = RTOT / 63 or (RH - RL) / 63, single pot.
(8) n = 0, 1, 2, ..., 63
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
3
Doc. No. MD-2010 Rev. K

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DP7409
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
ICC
ISB
ILI
ILO
VIL
VIH
VOL1
Parameter
Power Supply Current
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (VCC = 3.0V)
Test Conditions
fSCL = 400kHz
VIN = GND or VCC, SDA Open
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3 mA
Min
-1
VCC x 0.7
CAPACITANCE (1)
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol Test
CI/O Input/Output Capacitance (SDA)
CIN Input Capacitance (A0, A1, A2, A3, SCL, ¯W¯P¯)
Conditions
VI/O = 0V
VIN = 0V
Max
1
1
10
10
VCC x 0.3
VCC + 1.0
0.4
Max.
8
6
Units
mA
µA
µA
µA
V
V
V
Units
pF
pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
fSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can
start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
POWER UP TIMING (1)
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min Typ Max Units
400 kHz
50 ns
0.9 µs
1.2 µs
0.6 µs
1.2 µs
0.6 µs
0.6 µs
0 ns
100 ns
0.3 µs
300 ns
0.6 µs
50 ns
Max
1
1
Units
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2010 Rev. K
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Characteristics subject to change without notice

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DP7409
WRITE CYCLE LIMITS
Symbol Parameter
tWR Write Cycle Time
Max
5
Units
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1) (2)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
V
mA
Figure 1. Bus Timing
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
SDA
SCL
START CONDITION
STOP CONDITION
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
5
Doc. No. MD-2010 Rev. K