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Datasheet
Serial EEPROM Series Automotive EEPROM
125Operation SPI BUS EEPROM
BR25H320-2C
General Description
BR25H320-2C is a serial EEPROM of SPI BUS interface method.
Features
„ High speed clock action up to 10MHz (Max.)
„ Wait function by HOLDB terminal.
„ Part or whole of memory arrays settable as read only
memory area by program.
„ 2.55.5V single power source action most suitable
for battery use.
„ Page write mode useful for initial value write at
factory shipment.
„ For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1)
„ Self-timed programming cycle.
„ Low Supply Current
At Write Operation (5V)
: 1.0mA (Typ.)
At Read Operation (5V)
: 1.0mA (Typ.)
At Standby Operation (5V)
: 0.1μA (Typ.)
„ Address auto increment function at read operation
„ Prevention of write mistake
Write prohibition at power on.
Write prohibition by command code (WRDI).
Write prohibition by WPB pin.
Write prohibition block setting by status registers
(BP1, BP0).
Write mistake prevention function at low voltage.
„ MSOP8, TSSOP-B8, SOP8, SOP-J8 Package
„ Data at shipment Memory array: FFh, status register
WPEN, BP1, BP0 : 0
„ Data kept for 50 years (Ta125).
„ Data rewrite up to 300,000 times (Ta125).
„ AEC-Q100 Qualified.
Package
MSOP8
TSSOP-B8
2.90mm x 4.00mm x 0.90mm 3.00mm x 6.40mm x 1.20mm
Page write
Number of pages
Product Number
32 Byte
BR25H320-2C
SOP8
SOP-J8
5.00mm x 6.20mm x 1.71mm 4.90mm x 6.00mm x 1.65mm
BR25H320-2C
Capacity Bit Format
32Kbit
4Kx8
Product Number
BR25H320-2C
Supply Voltage
2.5~5.5V
MSOP8
TSSOP-B8
SOP8
SOP-J8
Product structureSilicon monolithic integrated circuit
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©2012 ROHM Co., Ltd. All rights reserved.
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This product is not designed protection against radioactive rays
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BR25H320-2C
Datasheet
Absolute maximum ratings (Ta=25°C)
Parameter
Symbol
Limits
Supply Voltage
Permissible Dissipation
VCC
Pd
-0.3~+6.5
380(MSOP8) *1
410(TSSOP-B8) *2
560(SOP8) *3
560(SOP-J8) *4
Storage Temperature Range
Tstg
-65+150
Operating Temperature Range
Topr
-40+125
Terminal Voltage
-0.3VCC+0.3
When using at Ta=25or higher, 3.1mW(*1) , 3.3mW(*2) , 4.5mW (*3,*4)to be reduced per 1
Memory cell characteristics (VCC=2.5V5.5V)
Parameter
Min.
Limits
Typ.
Max.
Write Cycles *5
1,000,000
500,000
300,000
Data Retention *5
100 - -
60 - -
*5: Not 100% TESTED
Recommended Operating Ratings
Parameter
50
Symbol
--
Limits
Supply Voltage
VCC
2.55.5
Input Voltage
Vin 0VCC
Input / output capacity (Ta=25°C, frequency=5MHz)
Parameter
Symbol
Input Capacity *6
CIN
Output Capacity *6
*6: Not 100% TESTED
COUT
Conditions
VIN=GND
VOUT=GND
Unit
V
mW
°C
°C
V
Unit
Cycles
Cycles
Cycles
Years
Years
Years
Unit
V
Min
Condition
Ta85°C
Ta105°C
Ta125°C
Ta25°C
Ta105°C
Ta125°C
Max
8
8
Unit
pF
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BR25H320-2C
Datasheet
DC Characteristics (Unless otherwise specified, Ta=-40~+125°C, VCC=2.5~5.5V)
Parameter
Symbol
Min.
Limits
Typ.
Unit Conditions
Max.
Input High Voltage
Input Low Voltage
VIH 0.7xVCC
VIL -0.3
VCC
+0.3
0.3x
VCC
V 2.5VCC5.5V
V 2.5VCC5.5V
Output Low Voltage
VOL
0
0.4 V IOL=2.1mA
Output High Voltage
VOH VCC-0.5
VCC V IOH=-0.4mA
Input Leakage Current ILI -2 2 μA VIN=0~VCC
Output Leakage Current ILO
-2
2 μA VOUT=0~VCC, CSB=VCC
VCC=2.5V,fSCK=5MHz, tE/W=4ms
ICC1
2.0 mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Byte write, Page write, Write status register
Supply Current (WRITE)
VCC=5.5V,fSCK=5 or 10 MHz, tE/W=4ms
ICC2
3.0 mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Byte write, Page write, Write status register
VCC=2.5V,fSCK=5MHz
ICC3
1.5 mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Read, Read status register
VCC=5.5V,fSCK=5MHz
Supply Current (READ) ICC4
2.0 mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Read, Read status register
VCC=5.5V,fSCK=10MHz
ICC5
4.0 mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Read, Read status register
Standby Current
VCC=5.5V
ISB - - 10 μA CSB=HOLDB=WPB=VCC, SCK=SI=VCC or =GND,
SO=OPEN
*Radiation resistance design is not made
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BR25H320-2C
Datasheet
AC Characteristics (Ta=-40~+125°C, unless otherwise specified, load capacity CL1=100pF)
Parameter
Symbol
2.5VCC5.5V
Min. Typ. Max.
4.5VCC5.5V
Min. Typ. Max.
SCK Frequency
fSCK
- - 5 - - 10
SCK High Time
tSCKWH
85 - - 40 - -
SCK Low Time
tSCKWL
85 - - 40 - -
CSB High Time
tCS 85 - - 40 - -
CSB Setup Time
tCSS
90 - - 30 - -
CSB Hold Time
tCSH
85 - - 30 - -
SCK Setup Time
tSCKS
90 - - 30 - -
SCK Hold Time
tSCKH
90 - - 30 - -
SI Setup Time
tDIS 20 - - 10 - -
SI Hold Time
tDIH
30 - - 10 - -
Data Output Delay Time1
Data Output Delay Time2
(CL2=30pF)
Output Hold Time
tPD1
tPD2
tOH
- - 60 - - 40
- - 50 - - 30
0 -- 0 --
Output Disable Time
tOZ - - 100 - - 40
HOLDB Setting
Setup Time
tHFS
0 -- 0 --
HOLDB Setting
Hold Time
tHFH
40 - - 30 - -
HOLDB Release
Setup Time
tHRS
0 -- 0 --
HOLDB Release
Hold Time
tHRH
70 - - 30 - -
Time from HOLDB
to Output High-Z
tHOZ
- - 100 - - 40
Time from HOLDB
to Output Change
SCK Rise Time*1
SCK Fall Time*1
OUTPUT Rise Time*1
OUTPUT Fall Time*1
tHPD
tRC
tFC
tRO
tFO
- - 60 - - 40
-- 1 -- 1
-- 1 -- 1
- - 40 - - 40
- - 40 - - 40
Write Time
*1 NOT 100% TESTED
tE/W
-- 4 -- 4
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
ns
ms
AC measurement conditions
Parameter
Symbol
Load Capacity 1
Load Capacity 2
Input Rise Time
Input Fall Time
Input Voltage
Input / Output
Judgment Voltage
CL1
CL2
Limits
Min. Typ. Max.
- - 100
- - 30
- - 50
- - 50
0.2VCC/0.8VCC
0.3VCC/0.7VCC
Unit
pF
pF
ns
ns
V
V
Input Voltage
0.8Vcc
Input/Output judgment voltage
0.7Vcc
0.2Vcc
0.3Vcc
Figure 1. Input/Output judgment voltage
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BR25H320-2C
Datasheet
Serial Input/Output Timing
CSB
SCK
tCS
tSCKS
tCSS
tSCKWL tSCKWH
tDIS tDIH
tRC tFC
SI
SO High-Z
Figure 2. Input timing
SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB.
tCS
CSB
tCSH tSCKH
SCK
SI
tPD tOH
SO
tRO,tFO tOZ
High-Z
Figure 3. Input / Output timing
SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB.
"H"
CSB
"L"
SCK
tHFS tHFH
SI n+1
SO Dn+1
tHOZ
Dn
tHRS tHRH
High-Z
tDIS
n
tHPD
Dn
n-1
Dn-1
HOLDB
Block diagram
CSB
SCK
SI
HOLDB
WPB
SO
Figure 4. HOLD timing
INSTRUCTION DECODE
CONTROL CLOCK
GENERATION
VOLTAGE
DETECTION
WRITE
INHIBITION
HIGH VOLTAGE
GENERATOR
INSTRUCTION
REGISTER
ADDRESS
REGISTER
12bit
DATA
REGISTER
8bit
STATUS REGISTER
ADDRESS
DECODER
12bit
READ/WRITE
AMP
8bit
32K
EEPROM
Figure 5. Block diagram
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©2012 ROHM Co., Ltd. All rights reserved.
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TSZ02201-0W1W0G100010-1-2
19.Dec.2012 Rev.003