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STB8N65M5, STD8N65M5, STF8N65M5,
STI8N65M5, STP8N65M5, STU8N65M5
N-channel 650 V, 0.56 Ω typ., 7 A MDmesh™ V Power MOSFET
in D²PAK, I²PAK, TO-220, TO-220FP, DPAK and IPAK packages
Datasheet — production data
Features
Type
STB8N65M5
STD8N65M5
STF8N65M5
STI8N65M5
STP8N65M5
STU8N65M5
VDSS @ RDS(on)
TJmax max.
ID
710 V < 0.6 Ω 7 A
PTOT
70 W
70 W
25 W
70 W
70 W
70 W
Worldwide best RDS(on) * area
Higher VDSS rating
High dv/dt capability
Excellent switching performance
Easy to drive
100% avalanche tested
Applications
Switching applications
3
2
1
TO-220FP
TAB
3
1
DPAK
TAB
3
2
1
TO-220
TAB
123
I²PAK
TAB
3
1
D²PAK
TAB
IPAK
3
2
1
Figure 1. Internal schematic diagram
$ 4!"
Description
These devices are N-channel MDmesh™ V
Power MOSFETs based on an innovative
proprietary vertical process technology, which is
combined with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The
resulting product has extremely low on-
resistance, which is unmatched among silicon-
based Power MOSFETs, making it especially
suitable for applications which require superior
power density and outstanding efficiency.
'
3
!-V
Table 1. Device summary
Order codes Marking Package Packaging
STB8N65M5
STD8N65M5
STF8N65M5
STI8N65M5
STP8N65M5
STU8N65M5
8N65M5
D²PAK
DPAK
TO-220FP
I²PAK
TO-220
IPAK
Tape and reel
Tape and reel
Tube
Tube
Tube
Tube
October 2012
This is information on a product in full production.
Doc ID 16531 Rev 5
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Contents
Contents
STB8N65M5, STD8N65M5, STF8N65M5 STI8N65M5, STP8N65M5, STU8N65M5
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves)
............................ 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26 Doc ID 16531 Rev 5

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STB8N65M5, STD8N65M5, STF8N65M5 STI8N65M5, STP8N65M5, STU8N65M5
1 Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Value
Symbol
Parameter
TO-220
D²PAK
I²PAK
IPAK
DPAK,
TO-220FP
Unit
VGS
ID
ID
IDM (2)
PTOT
IAR
EAS
dv/dt (3)
Gate- source voltage
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100 °C
Drain current (pulsed)
Total dissipation at TC = 25 °C
Max current during repetitive or single pulse
avalanche (pulse width limited by TJMAX)
Single pulse avalanche energy
(starting Tj = 25°C, ID = IAR, VDD = 50V)
Peak diode recovery voltage slope
VISO
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t = 1 s; TC = 25 °C)
Tstg Storage temperature
Tj Max. operating junction temperature
1. Limited by maximum junction temperature
2. Pulse width limited by safe operating area.
3. ISD 7 A, di/dt 400 A/µs, VDD 400 V, VDS(peak) < V(BR)DSS.
± 25
7
4.4
28
70
2
7 (1)
4.4 (1)
28 (1)
25
V
A
A
A
W
A
120 mJ
15 V/ns
2500
V
-55 to 150
150
°C
°C
Table 3. Thermal data
Symbol
Parameter
Value
Unit
DPAK IPAK TO-220 I²PAK D²PAK TO-220FP
Rthj-case
Thermal resistance
junction-case max
Rthj-amb
Thermal resistance
junction-ambient max
Rthj-pcb(1)
Thermal resistance
junction-pcb max
1.79
100 62.5
50
5 °C/W
62.5 °C/W
30 °C/W
1. When mounted on 1 inch² FR-4 board, 2oz Cu.
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Electrical characteristics
STB8N65M5, STD8N65M5, STF8N65M5 STI8N65M5, STP8N65M5, STU8N65M5
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4. On /off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source
breakdown voltage
ID = 1 mA, VGS = 0
IDSS
IGSS
VGS(th)
RDS(on
Zero gate voltage
VDS = 650 V
drain current (VGS = 0) VDS = 650 V, TC=125 °C
Gate-body leakage
current (VDS = 0)
VGS = ± 25 V
Gate threshold voltage VDS = VGS, ID = 250 µA
Static drain-source on-
resistance
VGS = 10 V, ID = 3.5 A
Min. Typ. Max. Unit
650 V
1 µA
100 µA
±100 nA
3 4 5V
0.56 0.60 Ω
Table 5.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0
690 pF
- 18 - pF
2 pF
Co(er)(1)
Equivalent output
capacitance energy
related
VGS = 0, VDS = 0 to 520 V
- 17 - pF
Co(tr)(2)
Equivalent output
capacitance time
related
VGS = 0, VDS = 0 to 520 V
- 52 - pF
RG
Intrinsic gate
resistance
f = 1 MHz open drain
2 4 6Ω
Qg Total gate charge
VDD = 520 V, ID = 3.5 A,
Qgs Gate-source charge VGS = 10 V
Qgd Gate-drain charge
(see Figure 19)
15 nC
- 3.6 - nC
6 nC
1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0
to 80% VDSS
2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0
to 80% VDSS
4/26 Doc ID 16531 Rev 5

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STB8N65M5, STD8N65M5, STF8N65M5 STI8N65M5, STP8N65M5, STU8N65M5 Electrical characteristics
Table 6. Switching times
Symbol
Parameter
td(off)
tr(V)
tc(off)
tf(i)
Turn-off delay time
Rise time
Cross time
Fall time
Test conditions
VDD = 400 V, ID = 4A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 20)
(see Figure 23)
Min. Typ. Max. Unit
50 ns
14 ns
--
20 ns
11 ns
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
ISD
ISDM (1)
VSD (2)
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD = 7 A, VGS = 0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 7 A, di/dt = 100 A/µs
VDD = 100 V
(see Figure 20)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 7 A, di/dt = 100 A/µs
VDD = 100 V, Tj = 150 °C
(see Figure 20)
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Min. Typ. Max. Unit
7A
-
28 A
- 1.5 V
200
- 1.6
16
ns
µC
A
263
- 1.9
15
ns
µC
A
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