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System PMIC for
Battery Powered Systems
BD71805MWV
General Description
The BD71805MWV is a single chip power management
IC for battery-powered portable devices. It integrates 4
Bucks, 3 LDOs, 2A single-cell linear charger, OVP,
Coulomb counter, RTC, 32 kHz crystal circuitry and 3
GPOs.
Four highly efficient 2.5MHz step-down converters
supply power to the application processor as well as
system peripherals such as DDR memory, wireless
modules, and touch controller. The regulator to the
processor core supports DVS. The regulators maintain
high efficiency over a wide range of current loads by
supporting both PFM and PWM modes. High switching
frequency allows the use of smaller and cheaper
inductors and capacitors.
Features
4 Buck Converters:
- 1-2000mA Buck
- 3-1000mA Bucks
3 LDOs (General purpose)
- 3-300mA LDOs
LDO for DDR Reference Voltage
LDO for Secure Non-Volatile Storage (SNVS)
Single-cell Linear LIB Charger with 30V-OVP
- Selectable Charging Voltage : 3.72 to 4.34 V
- Programmable Charge Current : 100 to 2000mA
- DCIN Over Voltage Protection
- Battery Over Voltage Protection
- Support Battery Supplement Mode
- Battery Short Circuit Detection
Voltage Measurement for Thermistor
- Bias Voltage Output for External Thermistor
Embedded Coulomb Counter for Battery Fuel
Gauging
- 15-bit ΔΣ-ADC with External Current Sense Resistor
(10 mΩ, ±1%)
- 1-sec cycle, 28-bit Accumulation
- Coulomb Count while Charging/Discharging
Battery Monitoring and Alarm Output
- Under Voltage Alarm while Discharging
- Over Discharge Current Alarm
- Over/Under Temperature Alarm
- Programmable Thresholds and Time Durations
- Automatic Low Voltage Mode (Battery Protection)
3.5V Detection :
Interrupt to Processor to Ask User Plug-in
3.3V Detection :
Interrupt to Processor to Indicate Battery Critically
Low Condition
Real Time Clock with 32.768kHz Crystal Oscillator
- 32.768kHz Clock Output
(Open Drain or CMOS Output Selectable)
3 GPOs (Open Drain or CMOS Output Selectable)
Power Control I/O
- Power On/Off Control Input
- Standby Input for Switching ON / STANDBY Mode
- Reset Input to Reset Hung PMIC
- Power On Reset Output
I2C Interface
Applications
E-Book Reader
Portable Media Players
Portable Navigation Devices
Key Specifications
Input Voltage Range (DCIN):
3.5V to 28V
Input Voltage Range (VIN,VSYS): 3.3V to 5.5V
Input Voltage Range (DVDD):
1.5V to 3.4V
Off Current :
25 μA (Typ)
[RTC+ Coulomb counter+ LDO_SNVS+ 32kOSC only]
Operating temperature range:
-40°C to +85°C
Package
UQFN64MV8080
W(Typ) D(Typ) H(Max)
8.0mm x 8.0mm x 1.0mm
Status of this document
The English version of this document is formal specification. A customer may use this translation version only for a reference to help
reading the formal version. If there are any differences in translation version of this document formal version takes priority.
Product structureSilicon monolithic integrated circuit
.www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
This product is not designed for protection against radioactive rays
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BD71805MWV
Typical Applications
Xtal
DCIN
PMIC
GPO
3.3V
3.3V
3.3V Touch
SD I/O
3.3V eMMC
WiFi
GPO
3-GPO
RTC
+
32kHz-OSC
Power ON/OFF
Sequencer
Coulomb
Counter
LIB Charger
OVP
BUCK3
BUCK1
LDO1
LDO_SNVS
(ON/OFF)
LDO2
LDO3
BUCK4
3.3V
3.3V
BUCK2
PWRON
GPO
3.3V
HIGH, NVCC33_IO
1.425V
i.MXARM,SOC, PU
1.2V
NVCC_1P2V
I2C
SNVS
(i.MX6SoloLite)
1.8V
NVCC18_IO
1.2V
NVCC_DRAM
POWER KEY
1.8V Core1
1.2V Core2
I/O
DDR
R 0.6V DVREF
(LPDDR2)
R (½*DVREFIN)
EPD
EPD
PMIC
Figure 1. Typical Applications 1 (Master Control Mode)
Xtal
DCIN
PMIC
GPO 3.15V
3.15V
Touch
3.15V WiFi I/O
GPO
3.15V
eMMC
SD
3-GPO
RTC
+
32kHz-OSC
Power ON/OFF
Sequencer
Coulomb
Counter
LIB Charger
OVP
BUCK3
BUCK 1,2
LDO1
LDO2
LDO3
LDO_SNVS
(Always on)
PWRON
BUCK4
DVREFIN
LDO_DVREF
GPO
3.15V HIGH, NVCC33
i.MX1.375V
2.5V
ARM, SOC, PU
1.8V
NVCC18
1.2V
NVCC12, NVCC_DRAM
3V SNVS (i.MX6SoloLite)
I2C
PMIC_ON_REQ
Power ON/OFF
Control
1.8V Core1
1.2V Core2
I/O
0.6V DVREF
(½*DVREFIN)
DDR
(LPDDR2)
POWER KEY
EPD
EPD
PMIC
Figure 2. Typical Applications 2 (Slave Control Mode)
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BD71805MWV
Block Diagram
BUCK4
10kΩ
GPO1
GPO2
GPO3
VDD_SNVS_IN
VOSNVS
SNVSCAP
1uF
18pF XIN32K
SEIKO-EPSON
FC-135
32.768kHz-Xtal
10kΩ
18pF XOUT32K
CLK32KOUT
2.7kΩ
DVDD
SDA
SCL
INTB
POR
VSYS
100kΩ
RESETINB
STANDBY
PWRON
MSSEL
DCIN
DCIN
1uF
VSYS
CHGLED
CPOUT
0.01uF
VSYS
4.7uF
UVLO
TSD
GPO
LDO_SNVS
3.0V
25mA
32kHz
OSC
RTC
I2C
SNVSCAP
10kΩ
POWER
CNT
Control
BUCK1
1.425V
2000mA
BUCK4
1.8V
1000mA
BUCK3
3.3V
1000mA
BUCK2
1.2V
1000mA
LDO_DVREF
DVREFIN*0.5 V
10mA
LDO1
1.2V
300mA
LDO2
3.3V
300mA
LDO3
3.3V
300mA
LIB-CHARGER
Ichg = 2A max
OVP<30V
Coulomb
Counter
PVIN1
LX1
FB1
4.7uF
2.2uH
PGND1
PVIN4
LX4
FB4
4.7uF
2.2uH
PGND4
PVIN3
LX3 4.7uF
FB3 2.2uH
PGND3
VSYS
BUCK1
VDD_ARM_IN
10uF
VDD_SOC_IN
VDD_PU_IN
VSYS
BUCK4
NVCC18_IO
LPDDR2(1.8V)
10uF
others
VSYS
BUCK3
10uF
VDD_HIGH_IN
NVCC33_IO
Wifi
eMMC
others
PVIN2
LX2
FB2
4.7uF
2.2uH
VSYS
BUCK2
10uF
NVCC_DRAM
LPDDR2(1.2V)
others
PGND2
DVREFIN
(N.C.)
VODVREF
(N.C.)
100kΩ
100kΩ
DDR-VREF
1uF
VINL1
1uF
VO1
1uF
VINL2
1uF
VO2
1uF
BUCK3
NVCC_1P2V
VSYS
IO(Default:OFF)
VO3
1uF
IO(Default:OFF)
VSYS
BAT
10uF
CHGREF
10uF
5.1kΩ
TS
TDK
NTCG163JF103FT1S
BATTP
BATTM
GNDCHG
VSYS
Battery pack
10mΩ
Figure 3. IC Block Diagram (Master Control Mode)
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BD71805MWV
Block Diagram - continued
VSYS
4.7uF
VO2
10kΩ
GPO1
GPO2
GPO3
VDD_SNVS_IN
100
VOSNVS
SNVSCAP
1uF
Coin 18pF XIN32K
SEIKO-EPSON
FC-135
32.768kHz-Xtal
VO2 18pF XOUT32K
10kΩ
CLK32KOUT
VO2
2.7kΩ
DVDD
SDA
SCL
INTB
POR
VSYS
DCIN
RESETINB
STANDBY
PWRON
MSSEL
DCIN
1uF
VSYS
CHGLED
CPOUT
0.01uF
UVLO
TSD
GPO
LDO_SNVS
3.0V
25mA
32kHz
OSC
RTC
I2C
SNVSCAP
10kΩ
POWER
CNT
Control
BUCK1
1.375V
2000mA
BUCK2
1.375V
1000mA
BUCK3
3.15V
1000mA
BUCK4
1.2V
1000mA
LDO_DVREF
DVREFIN*0.5 V
10mA
LDO1
2.5V
300mA
LDO2
1.8V
300mA
LDO3
1.2V
300mA
LIB-CHARGER
Ichg = 2A max
OVP<30V
Coulomb
Counter
PVIN1
LX1
FB1
4.7uF
2.2uH
PGND1
PVIN2
LX2
FB2
4.7uF
2.2uH
PGND2
PVIN3
LX3 4.7uF
FB3 2.2uH
PGND3
PVIN4
LX4
FB4
4.7uF
2.2uH
PGND4
DVREFIN
1uF
VSYS
BUCK1
VDD_ARM_IN
10uF
VSYS
BUCK2
VDD_SOC_IN
VDD_PU_IN
10uF
VSYS
BUCK3
10uF
VDD_HIGH_IN
NVCC_3V3_IN
Peripheral
EPD
VSYS
BUCK4
LPDDR2_core2
10uF
VODVREF
1uF
DDR-VREF
VINL1
1uF
VO1
1uF
VINL2
1uF
VO2
1uF
BUCK3
Peripheral
BUCK3
VO2
NVCC_18
LPDDR2_core1
VO3
1uF
NVCC_12
NVCC_DRAM
VSYS
BAT
10uF
CHGREF
10uF
5.1kΩ
VSYS
Battery pack
TS TDK
NTCG163JF103FT1S
BATTP
BATTM
GNDCHG
10mΩ
Figure 4. IC Block Diagram (Slave Control Mode)
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BD71805MWV
Pin Configuration
RESETINB
PGND2
FB2
GND
PWRON
STANDBY
MSSEL
GPO1
GPO2
GPO3
VODVREF
DVREFIN
CPOUT
FB4
PGND4
LX4
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32 PVIN1
31 PVIN1
30 VIN
29 VO3
28 VINL2
27 VO2
26 VO1
25 VINL1
24 INTB
23 POR
22 GNDT1
21 FB3
20 PGND3
19 PGND3
18 LX3
17 LX3
Figure 5. Pin Configuration (Top View)
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