MCP39F521.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 MCP39F521 데이타시트 다운로드

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MCP39F521
I2C Power Monitor with Calculation and Energy Accumulation
Features
• Power Monitoring Accuracy Capable of 0.1%
Error Across 4000:1 Dynamic Range
• Built-In Calculations on Fast 16-bit Processing
Core
- Active, Reactive, Apparent Power
- True Root Mean Square (RMS) Current,
RMS Voltage
- Line Frequency, Power Factor
• 64-bit Wide Import and Export Active Energy
Accumulation Registers
• 64-bit Four Quadrant Reactive Energy
Accumulation Registers
• Signed Active and Reactive Power Outputs
• Dedicated Zero Crossing Detection (ZCD) Pin
Output with Less than 100 µs Latency
• Automatic Event Pin Control through Fast Voltage
Surge Detection, Less than 5 ms Delay
• I2C Interface, up to 400 kHz Clock Rate
• Two Independent Registers for Minimum and
Maximum Output Quantity Tracking
• Fast Calibration Routines and Simplified
Command Protocol
• 512 Bytes User-Accessible EEPROM through
Page Read/Write Commands
• Low-Drift Internal Voltage Reference,
10 ppm/°C Typical
• 28-lead 5 x 5 mm QFN Package
• Extended Temperature Range -40°C to +125°C
Applications
• Power Monitoring for Home Automation
• Industrial Lighting Power Monitoring
• Real-Time Measurement of Input Power for
AC/DC Supplies
• Intelligent Power Distribution Units
Description
The MCP39F521 is a highly integrated, complete
single-phase power-monitoring device, designed for
real-time measurement of input power for AC/DC
power supplies, power distribution units, consumer and
industrial applications. It includes dual-channel
delta-sigma ADCs, a 16-bit calculation engine,
EEPROM and a flexible two-wire I2C interface.
An integrated low-drift voltage reference with
10 ppm/°C in addition to 94.5 dB of signal-to-noise and
distortion ratio (SINAD) performance on each
measurement channel allows for better than 0.1%
accurate designs across a 4000:1 dynamic range.
Package Types
MCP39F521
5x5 QFN*
28 27 26 25 24 23 22
EVENT 1
21 AGND
NC 2
20 AN_IN
NC 3
COMMONB 4
COMMONA 5
19 V1+
EP
29
18 V1-
17 I1-
OSCI 6
16 I1+
OSCO 7
15 A1
8 9 10 11 12 13 14
*Includes Exposed Thermal Pad (EP); see Table 3-1.
2015 Microchip Technology Inc.
DS20005442A-page 1

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MCP39F521
Functional Block Diagram
OSCI
OSCO
Timing
Generation
Internal
Oscillator
AVDD AGND
I1+ +
I1- -PGA
24-bit Delta-Sigma
Multi-Level
Modulator ADC
V1+
V1-
AN_IN
+
-PGA
24-bit Delta-Sigma
Multi-Level
Modulator ADC
10-bit SAR
ADC
DVDD DGND
16-BIT
CORE
FLASH
Calculation
Engine
(CE)
I2C
Serial
Interface
Digital Outputs
A1
A0
SCL
SDA
EVENT
ZCD
DS20005442A-page 2
2015 Microchip Technology Inc.

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MCP39F521
MCP39F521 Typical Application – Single-Phase, Two-Wire Application Schematic
LOAD
1 µF
+3.3V
10
0.1 µF
0.1 µF
+
2 m
-
1 k
33 nF
1 k
33 nF
1 k
33 nF
AVDD DVDD RESET
I1+ REFIN/OUT+
0.1 µF
I1- A1 To DVDD or GND, do not float
A0 To DVDD or GND, do not float
MCP39F521
V1-
3.3 DVDD
2 k
499 k499 k
V1+
SCL
3.3 DVDD
to MCU SCL
1 k
33 nF
N.C.
Leave Floating
Connect on PCB
+3.3V
NC
NC
NC
NC
DR
COMMONA,B
MCP9700A
AN_IN
SDA
EVENT
ZCD
2 k
to MCU SDA
(OPTIONAL)
22 pF
4 MHz
22 pF
OSCO
OSCI DGND
AGND
(OPTIONAL)
0.47 µ F 470
MCP1754
+3.3V
0.01 µF
470 µF
NL
DGND
AGND
Note:
The external sensing components shown here, a 2 mshunt, two 499 kand 1 kresistors for the
1000:1 voltage divider, are specifically chosen to match the default values for the calibration registers
defined in Section 6.0, Register Descriptions. By choosing low-tolerance components of these
values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero
calibration. See Section 8.0, MCP39F521 Calibration for more information.
2015 Microchip Technology Inc.
DS20005442A-page 3

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MCP39F521
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
DVDD .................................................................. -0.3 to +4.5V
AVDD .................................................................. -0.3 to +4.0V
Digital inputs and outputs w.r.t. AGND............... -0.3V to +4.0V
Analog Inputs (I+,I-,V+,V-) w.r.t. AGND ............... ....-2V to +2V
VREF input w.r.t. AGND ........................ ....-0.6V to AVDD +0.6V
Maximum Current out of DGND pin..............................300 mA
Maximum Current into DVDD pin .................................250 mA
Maximum Output Current Sunk by Digital IO ................25 mA
Maximum Current Sourced by Digital IO.......................25 mA
Storage temperature .....................................-65°C to +150°C
Ambient temperature with power applied......-40°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) .................4.0 kV, 200V
ESD on all other pins (HBM,MM) ........................4.0 kV, 200V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1.1 Specifications
TABLE 1-1: ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C
to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Power Measurement
Active Power (Note 1)
P
— ±0.1 — % 4000:1 Dynamic Range on
Current Channel (Note 2)
Reactive Power (Note 1)
Q
— ±0.1 — % 4000:1 Dynamic Range on
Current Channel (Note 2)
Apparent Power (Note 1)
S
— ±0.1 — % 4000:1 Dynamic Range on
Current Channel (Note 2)
Current RMS (Note 1)
IRMS
±0.1
— % 4000:1 Dynamic Range on
Current Channel (Note 2)
Voltage RMS (Note 1)
VRMS
±0.1
— % 4000:1 Dynamic Range on
Voltage Channel (Note 2)
Power Factor (Note 1)
— ±0.1 — %
Line Frequency (Note 1)
LF
— ±0.1 — %
Note 1:
2:
3:
4:
5:
6:
7:
Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 4 line cycles.
Specification by design and characterization; not production tested.
N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or
TCAL = 80 ms for 50 Hz line.
Applies to Voltage Sag and Voltage Surge events only.
Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical
Performance Curves for typical performance.
VIN = 1VPP = 353 mVRMS @ 50/60 Hz.
Variation applies to internal clock and I2C only. All calculated output quantities are temperature
compensated to the performance listed in the respective specification.
DS20005442A-page 4
2015 Microchip Technology Inc.

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MCP39F521
TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C
to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Calibration, Calculation and Event Detection Times
Auto-Calibration Time
tCAL
2N x (1/fLINE)
Minimum Time
for Voltage Surge/Sag
tAC_SASU
— see
Section 7.0
Detection
ms Note 3
ms Note 4
24-Bit Delta-Sigma ADC Performance
Analog Input
Absolute Voltage
VIN
-1
— +1 V
Analog Input
Leakage Current
Differential Input
Voltage Range
Offset Error
Offset Error Drift
AIN
(I1+ – I1-),
(V1+ – V1-)
VOS
-600/GAIN
-1
1 — nA
— +600/GAIN mV VREF = 1.2V,
proportional to VREF
— +1 mV
0.5 — µV/°C
Gain Error
Gain Error Drift
GE -4
— +4 % Note 5
— 1 — ppm/°C
Differential Input
Impedance
Signal-to-Noise
and Distortion Ratio
ZIN
SINAD
232
142
72
38
36
33
92
94.5
— kG = 1
— kG = 2
— kG = 4
— kG = 8
— kG = 16
— kG = 32
— dB Note 6
Total Harmonic Distortion
Signal-to-Noise Ratio
Spurious Free
Dynamic Range
Crosstalk
THD
SNR
SFDR
CTALK
92
-106.5
95
111
-122
-103
dBc Note 6
dB Note 6
dB Note 6
dB
AC Power
AC PSRR
-73
— dB AVDD and
Supply Rejection Ratio
DVDD = 3.3V + 0.6VPP,
100 Hz, 120 Hz, 1 kHz
DC Power
Supply Rejection Ratio
DC Common
Mode Rejection Ratio
DC PSRR
DC CMRR
-73
-105
— dB AVDD and DVDD = 3 to
3.6V
— dB VCM varies
from -1V to +1V
Note 1:
2:
3:
4:
5:
6:
7:
Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 4 line cycles.
Specification by design and characterization; not production tested.
N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or
TCAL = 80 ms for 50 Hz line.
Applies to Voltage Sag and Voltage Surge events only.
Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical
Performance Curves for typical performance.
VIN = 1VPP = 353 mVRMS @ 50/60 Hz.
Variation applies to internal clock and I2C only. All calculated output quantities are temperature
compensated to the performance listed in the respective specification.
2015 Microchip Technology Inc.
DS20005442A-page 5