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Data Sheet
CD22103A
January 1997 File Number 1310.3
CMOS HDB3 (High Density Bipolar 3)
Transcoder for 2.048/8.448Mb/s
Transmission Applications
The CD22103A is an LSI SOS integrated circuit which
performs the HDB3 transmission coding and reception
decoding functions with error detection. It is used in
2.048Mb/s and 8.448Mb/s transmission applications. The
CD22103A performs HDB3 coding and decoding for data
rates from 50Kb/s to 10Mb/s in a manner consistent with
CCITT G703 recommendations.
HDB3 transmission coding/reception decoding with code
error detection is performed in independent coder and
decoder sections. All transmitter and receiver inputs/outputs
are TTL compatible.
The HDB3 transmitter coder codes an NRZ binary unipolar
input signal (NRZ-IN) and a synchronous transmission clock
(CTX) into two HDB3 binary unipolar RZ output signals
(+HDB3 OUT, -HDB3 OUT). The TTL compatible output
signals +HDB3 OUT, -HDB3 OUT are externally mixed to
generate ternary bipolar HDB3 signals for driving
transmission lines.
The receiver decoder converts binary unipolar inputs
(+HDB3 IN, -HDB3 IN), which were externally split from
ternary bipolar HDB3 signals, and a synchronous clock
signal (CRX) into binary unipolar NRZ signals (NRZ-OUT).
The CD22103A operates with a 5V ±10% power supply
voltage over the full military temperature range at data rates
from 50Kb/s up to 10Mb/s.
Block Diagram
HDB3/AMI
CTX
NRZ-IN
ENCODER
IN
TRANSMITTER
CODER
LTE
+HDB3 OUT
-HDB3 OUT
CKR
+HDB3 IN
-HDB3 IN
CRX
DECODER
REQUIRES CLOCK
RECOVERY CIRCUIT
RECEIVER
DECODER NRZ-OUT
ERROR
DETECT
ERR
RAIS
AIS
DETECT
AIS
Features
• HDB3 Coding and Decoding for Data Rates from 50Kb/s
to 10Mb/s in a Manner Consistent with CCITT G703
Recommendations
• HDB3/AMI Transmission Coding/Reception Decoding with
Code Error Detection is Performed in Independent Coder
and Decoder Sections
• All Transmitter and Receiver Inputs/Outputs are TTL
Compatible
• Internal Loop Test Capability
• Pin and Functionally Compatible with Type MJ1471
Ordering Information
PART
NUMBER
CD22103AD
CD22103AE
TEMP. RANGE
(oC) PACKAGE
-55 to 125 16 Ld SBDIP
-40 to 85 16 Ld PDIP
PKG. NO.
D16.3
E16.3
Pinout
CD22103A (PDIP, SBDIP)
TOP VIEW
NRZ-IN 1
CTX 2
HDB3/AMI 3
NRZ-OUT 4
CRX 5
RAIS 6
AIS 7
VSS 8
16 VDD
15 +HDB3 OUT
14 -HDB3 OUT
13 +HDB3 IN
12 LTE
11 -HDB3 IN
10 CKR
9 ERR
68 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

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CD22103A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD)
(Voltages referenced to VSS Terminal) . . . . . . . . . . . . . -0.5 to 8V
Supply Voltage Range
For TA = Full Package Temperature Range . . . . . . . . . . . . 4.5V to 5.5V
Input Voltage (All Inputs) . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5V
Input Current (Any One Input) . . . . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Power Dissipation
For TA = -40oC to 60oC (Package Type E). . . . . . . . . . . . .500mW
For TA = 60oC to 85oC
(Package Type E) . . . . . . . .
Derate Linearly 12mW/oC to 200mW
For
For
TA
TA
=
=
-55oC to 100oC (Package
100oC to 125oC
Type
D).
.
.
.
.
.
.
.
.
.
.
.500mW
(Package Type D) . . . . . . . . Derate Linearly 12mW/oC to 200mW
Device Dissipation per Output Transistor
For TA = Full Package Temperature Range (All Types) . . . . . 100mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . -65oC TA 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range
Package
Package
Type
Type
D
E
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-.5-54o0CoC≤≤TATA≤≤12855ooCC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications VDD = 5V ±10%, TA = 25oC
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
STATIC SPECIFICATIONS
Quiescent Device Current
Operating Device Current
HDB3 Output Low (Sink) Current
HDB3 Output High (Source) Current
All Other Outputs Low (Sink) Current
All Other Outputs High (Source) Current
Input Low Current
Input High Current
Input Low Voltage
Input High Voltage
Input Capacitance
IDD
IOL1
IOH1
IOL2
IOH2
IIL
IIH
VIL
VIH
IIN
fCL = 10MHz
VOL = 0.5V
VOH = 2.8V
VOL = 0.5V
VOH = 2.8V
- - 100 µA
- - 8 mA
1.6 -
- mA
-10 -
- mA
1.6 -
- mA
-1.6 -
- mA
- - -1 µA
- - 1 µA
- - 0.8 V
2- -V
- - 5 pF
Electrical Specifications TA = -40oC to 85oC for Plastic Package; -55oC to 125oC for Ceramic Package; VDD = 4.5V to 5.5V;
CL = 15pF
PARAMETER
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
DYNAMIC INPUT
CTX, CRX Input Frequency
CTX, CRX Input Rise Time
Fall Time
NRZ-IN to CTX
Data Setup Time
Data Hold Time
HDB3 IN to CRX
Data Setup Time
Data Hold Time
fCTX, fCRX
tRCL
tFCL
tS
tH
tS
tH
3
3
3
3
4
3
0.05
-
-
15
15
15
0
-
-
-
-
-
-
-
10 MHz
1 µs
1 µs
- ns
- ns
- ns
- ns
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CD22103A
Electrical Specifications TA = -40oC to 85oC for Plastic Package; -55oC to 125oC for Ceramic Package; VDD = 4.5V to 5.5V;
CL = 15pF (Continued)
PARAMETER
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
CRX to CKR (CRX = 8.448MHz)
Pretrigger
Delay
DYNAMIC OUTPUT
tP 5 - - 20 ns
tD 5 - - 20 ns
Transmitter Coder, CTX to HDB3 OUT:
Data Propagation Delay Time
Handling Delay Time
HDB3 OUT Output Pulse Width
(Clock duty cycle = 50%)
fCL = 2.048MHz
fCL = 8.448MHz
Receiver Decoder
CRX to NRZ OUT:
Data Propagation Delay Times
Handling Delay Time
HDB3 IN to CKR
HDB3 Propagation Delay Time
LTE = 0
LTE = 1
tDD 3 - - 90 ns
tHD 1 - 4 - Clock Period
tW 3 238 - 260 ns
tW 3 53 - 65
tDD 4 - - 90 ns
tHD 2 - 4 - Clock Period
tIN CKR
4
-
- 65 ns
4 - - 30 ns
Functional Description
The CD22103A is designed to code and decode HDB3
signals which are coded as binary digital signals (NRZ-lN)
and (+HDB3 IN, -HDB3 IN), accompanied by sampling
clocks (CTX) and (CRX). The two binary coded HDB3 out-
puts, (+HDB3 OUT, -HDB3 OUT) may be externally mixed to
create the ternary HDB3 signals (See Figure 1).
The two binary HDB3 input signals have been split from the
input ternary HDB3 in an external line receiver.
The receiver decoder converts binary unipolar inputs (+HDB3 IN,
-HDB3 IN), which were externally split from ternary bipolar HDB3
signals, and a synchronous clock signal (CRX) into binary unipolar
NRZ signals (NRZ-OUT).
Received signals not consistent with HDB3 coding rules are
detected as errors. The receiver error output (ERR) is active high
during one CRX period of each bit of received data that is inconsis-
tent with HDB3 coding rules.
An input string consisting of all ones (or marks) is detected and
signaled by a high level at the Alarm Signal (AIS) output. The AIS
output is set to a high level when less than three zeros are
received during two consecutive periods of the Reset Alarm Inhibit
Signal (RAIS). The AIS output is subsequently reset to a low level
when three or more zeros are received during two periods of the
reset signal (RAIS).
A diagnostic Loop-Test Mode may be entered by driving the Loop
Test Enable Input (LTE) high. In this mode the HDB3 transmitter
outputs (+HDB3 OUT, -HDB3 OUT) are internally connected to
70
the HDB3 receiver inputs, and the external HDB3 receiver inputs,
and the external HDB3 receiver inputs (+HDB3 IN, -HDB3 IN) are
disabled. The NRZ binary output signal (NRZ - OUT) corresponds
to the NRZ binary input signal (NRZ - IN) delayed by approxi-
mately 8 clock periods.
The Clock Receiver Output (CKR) is the product of the two HDB3
input signals or-ed together. The CRX clock signal may be derived
from the CKR signal with external clock extraction circuitry. In the
Loop Test Mode (LTE = 1) CKR is the product of the +HDB3 OUT
and -HDB3 OUT signals or-ed together.
The CD22103A may also be used to perform the AMI to NRZ
coding/decoding function. To use the CD22103A in this mode, the
HDB3/AMI control input is driven low.
Error Detection
Received HDB3/AMl binary input signals are checked for
coding violations, and an error signal (ERR) is generated as
described below.
• HDB3 Signals HDB3/AMl = High
The error signal (ERR) is flagged high for one CTX period if
a violation pulse (±V) is received of the same polarity as the
last received violation pulse.
A violation pulse (±V) is considered a reception error and
does not cause replacement of the last string of 4 bits to
zeros, if:

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CD22103A
The received 4 data bits previous to reception of the violation
pulse have not been the sequence BX00 (where X = don't
care). The error signal (ERR) remains low.
NOTES:
1. The data sequences B000V and BB00V are valid HDB3 codings
of the NRZ binary sequence 10000.
2. The error signal (ERR) count, is the accurate number of all single
bit errors.
• AMl Signals HDB3/AMl = Low
- A coding error (ERR) is signaled when a violation pulse
(+V) is received.
• In Either the HDB3 or AMI Mode
- When high levels appear simultaneously on both HDB3
inputs (+ HDB3 IN, -HDB3 IN) a logical one is assumed
in the HDB3/AMl input stream and the error signal
(ERR) goes high for the duration of the violation.
Alarm Inhibit Signal
- The alarm output (AIS) is set high if, in two successive
periods of the external Reset Alarm Signal (RAlS), less
than three zeros are received.
- The alarm output (AlS) is reset low when three or more
zeros are received during two Reset Alarm Signal periods.
Transcoder Operation
Transmitter Coder (See Figure 1)
The HDB3/AMI transmitter coder operates on 4-bit serial
strings of NRZ binary data and a synchronous transmitter
clock (CTX). NRZ binary data is serially clocked into the
transmitter on the negative transition of the (CTX) clock.
HDB3/AMI coding is performed on the 4-bit string, and
HDB3/AMI binary output data is clocked out to the (+HDB3
OUT, -HDB3 OUT) outputs on the positive transition of the
transmitter clock (CTX) 3 1/2 clock pulses after the data
appeared at the (NRZ-IN) input.
Receiver Decoder (See Figure 2)
The HDB3/AMI receiver decoder operates on 4-bit serial
strings of binary coded HDB3/AMI signals, and a synchro-
nous receiver clock (CRX), HDB3/AMI binary data is serially
clocked into the receiver on the positive transition of the
(CRX) clock. HDB3/AMI decoding is performed on the 4-bit
string, and NRZ binary output data is clocked out to the
(NRZ-OUT) output on the positive transition of the receiver
clock (CRX) 4 clock pulses after the data appeared at the
(+HDB3 IN, -HDB3 IN) inputs.
HANDLING DELAY
CTX
NRZ - IN
+HDB3 OUT
HDB3
CODED
-HDB3 OUT
EXTERNAL GENERATED
TERNERY HDB3
+HDB3 OUT
AMI
CODED
-HDB3 OUT
EXTERNAL GENERATED
AMI
FIGURE 1. TRANSMITTER CODER OPERATION TIMING WAVEFORMS - NRZ TO HDB3/AMI CODING
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CD22103A
HDB3 RECEIVED SIGNAL
EXTERNALLY
SPLIT
+HDB3 IN
-HDB3 IN
CKR
EXTERNALLY
GENERATED
CRX
HANDLING DELAY
NRZ - OUT
FIGURE 2. RECEIVER DECODER OPERATION TIMING WAVEFORMS - HDB3 TO NRZ DECODING
CTX
NRZ - IN
+HDB3 OUT
OR
-HDB3 OUT
tRCL
90%
10%
tS
tFCL
50%
tDD
tWCL
tH
tW
FIGURE 3. TRANSMITTER CODER TIMING WAVEFORMS
CRX
10%
tFCL
90%
50%
tS
tRCL
50%
+HDB3 IN
-HDB3 IN
tINCKR
CKR
tDD
NRZ - OUT
tWCL
tH
50%
50%
50%
tW
50%
FIGURE 4. INPUT REQUIREMENTS AND OUTPUT CHARACTERISTICS
72