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MC74HC573A
Octal 3-State Noninverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The MC74HC573A is identical in pinout to the LS573. The devices
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The HC573A is identical in function to the HC373A but has the data
inputs on the opposite side of the package from the outputs to facilitate
PC board layout.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
In Compliance with the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 218 FETs or 54.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
DATA
INPUTS
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
NONINVERTING
OUTPUTS
LATCH ENABLE 11
OUTPUT ENABLE 1
PIN 20 = VCC
PIN 10 = GND
Design Criteria
Internal Gate Count*
Value
54.5
Internal Gate Progation Delay
Internal Gate Power Dissipation
1.5
5.0
Speed Power Product
0.0075
*Equivalent to a two−input NAND gate.
Units
ea.
ns
mW
pJ
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 16
1
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SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LATCH
ENABLE
MARKING DIAGRAMS
20
74HC573A
AWLYYWWG
20
HC
573A
ALYWG
G
11
SOIC−20
TSSOP−20
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output Latch
Enable Enable
D
Output
Q
L HH
L HL
L LX
H XX
X = Don’t Care
Z = High Impedance
H
L
No Change
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
MC74HC573A/D

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MC74HC573A
ÎÎMÎÎSAymXÎÎIbMolUÎÎM RÎÎATÎÎINGÎÎS ÎÎÎÎPaÎÎramÎÎeterÎÎÎÎÎÎÎÎÎÎÎÎÎÎVÎÎalueÎÎÎÎÎÎUnÎÎit
VCC DC Supply Voltage (Referenced to GND)
–0.5 to +7.0
V
Vin DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin
±20 mA
Iout DC Output Current, per Pin
±35 mA
ICC DC Supply Current, VCC and GND Pins
±75 mA
PD Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
mW
Tstg Storage Temperature
TL Lead Temperature, 1 mm from Case for 10 Seconds
(TSSOP or SOIC Package)
–65 to +150
260
_C
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/°C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max Unit
VCC DC Supply Voltage (Referenced to GND)
2.0 6.0
V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND)
0 VCC V
TA Operating Temperature, All Package Types
–55 +125
_C
tr, tf Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
VIH Minimum High−Level Input Voltage
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
VOH Minimum High−Level Output
Voltage
VOL Maximum Low−Level Output
Voltage
Iin Maximum Input Leakage Current
IOZ Maximum Three−State Leakage
Current
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VIH or VIL
|Iout| v 20 mA
Vin = VIH or VIL
|Iout| 2.4mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
Vin = VIH or VIL
|Iout| 2.4mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VCC or GND
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
Vin = VCC or GND
IIoutI = 0 mA
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
6.0
Guaranteed Limit
–55 to
25_C
v85_C v125_C
1.5 1.5 1.5
2.1 2.1 2.1
3.15 3.15 3.15
4.2 4.2 4.2
0.5 0.5 0.5
0.9 0.9 0.9
1.35 1.35 1.35
1.8 1 8 1.8
1.9 1.9 1.9
4.4 4.4 4.4
5.9 5.9 5.9
2.48 2.34
3.98 3.84
5.48 5.34
2.2
3.7
5.2
0.1 0.1 0.1
0.1 0.1 0.1
0.1 0.1 0.1
0.26 0.33
0.26 0.33
0.26 0.33
0.4
0.4
0.4
±0.1 ±1.0 ± .0
–0.5 –5.0 –10
Unit
V
V
V
V
mA
mA
4.0 40 160 mA
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MC74HC573A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
tPLH,
tPHL
Parameter
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
VCC
V
2.0
3.0
4.5
6.0
tPLH,
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
3.0
4.5
6.0
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
4.5
6.0
Cin Maximum Input Capacitance
Cout Maximum 3−State Output Capacitance (Output in High−Impedance State)
Guaranteed Limit
–55 to 25_C v85_C v125_C
150 190 225
100 140 180
30 38 45
26 33 38
160 200 240
105 145 190
32 40 48
27 34 41
150 190 225
100 125 150
30 38 45
26 33 38
150 190 225
100 125 150
30 38 45
26 33 38
60 75 90
27 32 36
12 15 18
10 13 15
10 10 10
15 15 15
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Enabled Output)*
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
23
Unit
ns
ns
ns
ns
ns
pF
pF
pF
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
tsu Minimum Setup Time, Input D to Latch Enable
th Minimum Hold Time, Latch Enable to Input D
tw Minimum Pulse Width, Latch Enable
tr, tf Maximum Input Rise and Fall Times
Figure
4
4
2
1
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25_C
v85_C
v125_C
Min Max Min Max Min Max
50 65
40 50
10 13
9.0 11
75
60
15
13
5.0 5.0 5.0
5.0 5.0 5.0
5.0 5.0 5.0
5.0 5.0 5.0
75 95 110
60 80 90
15 19 22
13 16 19
1000
800
500
400
1000
800
500
400
1000
800
500
400
Unit
ns
ns
ns
ns
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tr
INPUT D
tPLH
Q
90%
50%
10%
90%
50%
10%
tTLH
MC74HC573A
SWITCHING WAVEFORMS
tf
VCC
GND
tPHL
tTHL
LATCH
ENABLE
50%
tw
tPLH
Q 50%
tPHL
VCC
GND
OUTPUT
ENABLE
Q
Q
Figure 1.
50%
tPZL tPLZ
VM
tPZH
VM
tPHZ
10%
90%
MC74HC573A: VM = VOH x 0.5
MC74HCT573A: VM = 1.3 V @ VCC = 3 V
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
Figure 3.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6. Test Circuit
INPUT D
LATCH
ENABLE
Figure 2.
VALID
50%
tSU th
50%
VCC
GND
VCC
GND
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
LATCH ENABLE 11
OUTPUT ENABLE 1
Figure 4.
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
Figure 7. EXPANDED LOGIC DIAGRAM
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MC74HC573A
ORDERING INFORMATION
Device
Package
Shipping
MC74HC573ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HC573ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
MC74HC573ADTG
TSSOP−20
(Pb−Free)
75 Units / Rail
MC74HC573ADTR2G
TSSOP−20
(Pb−Free)
2500 Tape & Reel
NLV74HC573ADTR2G*
TSSOP−20
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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