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INTEGRATED CIRCUITS
FB2031
9-bit latched/registered/pass-thru
Futurebus+ transceiver
Product specification
IC19 Data Handbook
1995 May 25
Philips
Semiconductors

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Philips Semiconductors
9-bit latched/registered/pass-thru Futurebus+ transceiver
Product specification
FB2031
FEATURES
Latched, registered or straight through in
either A to B or B to A path
Drives heavily loaded backplanes with
equivalent load impedances down to 10.
High drive 100mA BTL open collector
drivers on B-port
Allows incident wave switching in heavily
loaded backplane buses
Reduced BTL voltage swing produces less
noise and reduces power consumption
Built-in precision band-gap reference
provides accurate receiver thresholds and
improved noise immunity
Compatible with IEEE Futurebus+ or
proprietary BTL backplanes
Each BTL driver has a dedicated Bus GND
for a signal return
Controlled output ramp and multiple GND
pins minimize ground bounce
Glitch-free power up/power down operation
Low ICC current
Tight output skew
Supports live insertion
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH Propagation delay
tPHL
An to Bn
tPLH Propagation delay
tPHL
Bn to An
CO Output capacitance (B0 – Bn only)
IOL Output current (B0 – Bn only)
ICC Supply current
AIn to Bn
(outputs Low or High)
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
TYPICAL
2.7
4.4
4.2
6
100
17
50
25
UNIT
ns
ns
pF
mA
mA
mA
ORDERING INFORMATION
PACKAGE
52-pin Plastic Quad Flat Pack (QFP)
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0°C to +70°C
FB2031BB
INDUSTRIAL RANGE
VCC = 5V±10%; Tamb = –40°C to +85°C
CD3206BB
DRAWING
NUMBER
SOT379-1
PIN CONFIGURATION
1995 May 25
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
A2
LOGIC GND
A3
LOGIC GND
1
2
3
4
5
A4 6
LOGIC GND 7
A5 8
LOGIC GND 9
A6 10
LOGIC GND 11
A7 12
LOGIC GND 13
9-Bit latched/registered transceiver
FB2031
52-lead PQFP
39 BUS GND
38 B1
37 BUS GND
36 B2
35 BUS GND
34 B3
33 BUS GND
32 B4
31 BUS GND
30 B5
29 BUS GND
28 B6
27 BUS GND
14 15 16 17 18 19 20 21 22 23 24 25 26
SG00060
2
853-1714 15279

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Philips Semiconductors
9-bit latched/registered/pass-thru Futurebus+ transceiver
Product specification
FB2031
DESCRIPTION
The FB2031 is a 9-bit latched/registered
transceiver featuring a latched, registered or
pass-thru mode in either the A-to-B or B-to-A
direction. The FB2031 is intended to provide
the electrical interface to a high performance
wired-OR bus.
The TTL-level side (A port) has a common
I/O. The common I/O, open collector B port
operates at BTL signal levels. The logic
element for data flow in each direction is
controlled by two mode select inputs (SEL0
and SEL1). A “00” configures latches in both
directions. A “10” configures thru mode in
both directions. A “01” configures register
mode in both directions. A “11” configures
register mode in the A-to-B direction and
latch mode in the B-to-A direction.
When configured in the buffer mode, the
inverse of the input data appears at the
output port. In the register mode, data is
stored on the rising edge of the appropriate
clock input (LCAB or LCBA). In the latch
mode, clock pins serve as transparent-Low
latch enables. Regardless of the mode, data
is inverted from input to output.
The 3-State A port is enabled by asserting a
High level on OEA. The B port has two output
enables, OEB0 and OEB1. Only when OEB0
is High and OEB1 is Low is the output
enabled.
When either OEB0 is Low or OEB1 is High,
the B port is inactive and is pulled to the level
of the pullup voltage. New data can be
entered in the register and latched modes or
can be retained while the associated outputs
are in 3-State (A port) or inactive (B port).
The B-port drivers are Low-capacitance open
collectors with controlled ramp and are
designed to sink 100mA. Precision band gap
references on the B-port insure very good
noise margins by limiting the switching
threshold to a narrow region centered at
1.55V.
The B-port interfaces to “Backplane
Transceiver Logic” (see the IEEE 1194.1 BTL
standard). BTL features low power
consumption by reducing voltage swing (1V
p-p, between 1V and 2V) and reduced
capacitive loading by placing an internal
series diode on the drivers. BTL also
provides incident wave switching, a necessity
for high performance backplanes.
Output clamps are provided on the BTL
outputs to further reduce switching noise.
The “VOH” clamp reduces inductive ringing
effects during a Low-to-High transition. The
“VOH” clamp is always active. The other
clamp, the “trapped reflection” clamp, clamps
out ringing below the BTL 0.5V VOL level.
This clamp remains active for approximately
100ns after a High-to-Low transition.
PACKAGE THERMAL CHARACTERISTICS
PARAMETER
CONDITION
θja Still air
θja 300 Linear feet per minute air flow
θjc Thermally mounted on one side to heat sink
To support live insertion, OEB0 is held Low
during power on/off cycles to insure glitch-
free B port drivers. Proper bias for B port
drivers during live insertion is provided by the
BIAS V pin when at a 5V level while VCC is
Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series
Schottky diode, and also bias the B port
output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with
IEEE BTL Standard 1194.1. If live insertion is
not a requirement, the BIAS V pin should be
tied to a VCC pin.
The LOGIC GND and BUS GND pins are
isolated inside the package to minimize noise
coupling between the BTL and TTL sides.
These pins should be tied to a common
ground external to the package.
Each BTL driver has an associated BUS
GND pin that acts as a signal return path and
these BUS GND pins are internally isolated
from each other. In the event of a ground
return fault, a “hard” signal failure occurs
instead of a pattern dependent error that may
be infrequent and impossible to troubleshoot.
As with any high power device, thermal
considerations are critical. It is
recommended that airflow (300Ifpm)
and/or thermal mounting be used to
ensure proper junction temperature.
52-PIN PLASTIC QFP
80°C/W
58°C/W
20°C/W
PIN DESCRIPTION
SYMBOL
PIN NUMBER
A0 – A8
50, 52, 2, 4, 6, 8, 10, 12, 14
B0 – B8
40, 38, 36, 34, 32,
30, 28, 26, 24
OEB0
46
OEB1
45
OEA
47
BUS GND
25, 27, 29, 31, 33,
35, 37, 39, 41
LOGIC GND
51, 1, 3, 5, 7, 9, 11, 13
VCC
BIAS V
23, 43, 49
48
BG VCC
BG GND
17
19
SEL0
20
SEL1
15
LCAB
18
LCBA
16
TMS
42
TCK
44
TDI 22
TDO
21
TYPE
I/O
I/O
Input
Input
Input
GND
GND
Power
Power
Power
GND
Input
Input
Input
Input
Input
Input
Input
Output
NAME AND FUNCTION
BiCMOS data inputs/3-State outputs (TTL)
Data inputs/Open Collector outputs, High current drive (BTL)
Enables the B outputs when High
Enables the B outputs when Low
Enables the A outputs when High
Bus ground (0V)
Logic ground (0V)
Positive supply voltage
Live insertion pre-bias pin
Band Gap threshold voltage reference
Band Gap threshold voltage reference ground
Mode select
Mode select
A to B clock/latch enable (transparent latch when Low)
B to A clock/latch enable (transparent latch when Low)
Test Mode Select (optional, if not implemented then no connect)
Test Clock (optional, if not implemented then no connect)
Test Data In (optional, if not implemented then no connect)
Test Data Out (optional, if not implemented then shorted to TDI)
1995 May 25
3

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Philips Semiconductors
9-bit latched/registered/pass-thru Futurebus+ transceiver
Product specification
FB2031
FUNCTION TABLE
MODE
An to Bn thru mode
An to Bn transparent latch
An to Bn latch and read
Bn outputs latched and read
(preconditioned latch)
An to Bn register
Bn to An thru mode
Bn to An transparent latch
Bn to An latch and read
An outputs latched and read
(preconditioned latch)
Bn to An register
Disable Bn outputs
Disable An outputs
INPUTS
OUTPUTS
An Bn* OEB0 OEB1 OEA LCAB LCBA SEL0 SEL1 An
Bn
L —H L L X X H
L input H**
H—H L L X X H
L input L
L — H L L L X L L input H**
H—H
L
L
L
X
L
L input L
l — H L L X L L input H**
h — H L L X L L input L
X—H L X H X
L
L
X
latched
data
l — H L L X X H input H**
h — H L L X X H input L
—L
Disable
H X X H L H input
—H
Disable
HXX H
L
L input
—L
Disable
H X L L L H input
— H Disable H X L L L L input
—L
Disable
H X L H H H input
—H
Disable
H X L H H L input
—l
Disable
HX L
L H input
—h
Disable
HX L L
L input
—l
Disable
H X H H H input
—h
Disable
H X H H L input
—X X X H X H L
L
latched
data
X
—X X X H X H H
H
latched
data
X
—l
Disable
H X L H H input
—h
Disable
H X L H L input
X X L X X X X X X X H**
X X X H X X X X X X H**
XXXXL X X X X Z X
FUNCTION SELECT TABLE
MODE SELECTED
Thru mode
Register mode (An to Bn)
Latch mode (An to Bn)
Register mode (Bn to An)
Latch mode (Bn to An)
NOTES:
H = High voltage level
L = Low voltage level
l = Low voltage level one set-up time
prior to the Low-to-High LCXX transition
h = High voltage level one set-up time
prior to the Low-to-High LCXX transition
SEL0
H
X
L
L
L
H
X=
Z=
—=
=
H** =
Don’t care
High-impedance (OFF) state
Input not externally driven
Low-to-High transition
Goes to level of pull-up voltage
SEL1
L
H
L
H
L
H
Bn* = Precaution should be taken to
ensure B inputs do not float. If they do, they
are equal to Low state.
Disable = OEB0 is Low or OEB1 is High.
1995 May 25
4

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Philips Semiconductors
9-bit latched/registered/pass-thru Futurebus+ transceiver
Product specification
FB2031
LOGIC DIAGRAM
OEB0 46
45
OEB1
OEA 47
A8 14
A7 12
10
TTL
8
6
4
2
52
A1
A0 50
LCAB 18
SEL0 20
SEL1 15
LCBA 16
DQ
E
DQ
Clk
MUX
AB
MUX
AB
DQ
E
DQ
Clk
MUX
AB
QQ DD
E
QD
Clk
MUX
AB
DQ
E
DQ
Clk
MUX
AB
QD
E
QD
Clk
MUX
AB
DQ
E
DQ
Clk
MUX
AB
QD
E
QD
Clk
MUX
AB
Decode
In Out
QD
E
QD
Clk
24 B8
26
B7
28
30
32 BTL
34
36
38 B1
40
B0
TMS
TCK
TDI
TDO
42
44
22
21
(JTAG Boundary Scan pins)
LOGIC GND
BUS GND
BIAS V
VCC
BG VCC
BG GND
= 1, 3, 5, 7, 9, 11, 13, 51
= 25, 27, 29, 31, 33, 35, 37, 39, 41
= 48
= 23, 43, 49
= 17
= 19
SG00061
1995 May 25
5