ADuC843.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 ADuC843 데이타시트 다운로드

No Preview Available !

Data Sheet
MicroConverter 12-Bit ADCs and DACs with
Embedded High Speed 62 kB Flash MCU
ADuC841/ADuC842/ADuC843
FEATURES
Pin compatible upgrade of ADuC812/ADuC831/ADuC832
Increased performance
Single-cycle 20 MIPS 8052 core
High speed 420 kSPS 12-bit ADC
Increased memory
Up to 62 kBytes on-chip Flash/EE program memory
4 kBytes on-chip Flash/EE data memory
In-circuit reprogrammable
Flash/EE, 100 year retention, 100 kCycle endurance
2304 bytes on-chip data RAM
Smaller package
8 mm × 8 mm chip scale package
52-lead PQFP—pin-compatible upgrade
Analog I/O
8-channel, 420 kSPS high accuracy, 12-bit ADC
On-chip, 15 ppm/°C voltage reference
DMA controller, high speed ADC-to-RAM capture
Two 12-bit voltage output DACs1
Dual output PWM ∑-∆ DACs
On-chip temperature monitor function
8052 based core
8051 compatible instruction set (20 MHz max)
High performance single-cycle core
32 kHz external crystal, on-chip programmable PLL
12 interrupt sources, 2 priority levels
Dual data pointers, extended 11-bit stack pointer
On-chip peripherals
Time interval counter (TIC)
UART, I2C®, and SPI® Serial I/O
Watchdog timer (WDT)
Power supply monitor (PSM)
Power
Normal: 4.5 mA @ 3 V (core CLK = 2.098 MHz)
Power-down: 10 μA @ 3 V2
Development tools
Low cost, comprehensive development system
incorporating nonintrusive single-pin emulation,
IDE based assembly and C source debugging
APPLICATIONS
Optical networking—laser power control
Base station systems
Precision instrumentation, smart sensors
Transient capture systems
DAS and communications systems
1 ADuC841/ADuC842 only.
2 ADuC842/ADuC843 only, ADuC841 driven directly by external crystal.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
ADuC841/ADuC842/ADuC843
12-BIT
DAC
BUF
DAC1
ADC0
ADC1
ADC5
ADC6
ADC7
MUX
T/H
TEMP
SENSOR
12-BIT ADC
HARDWARE
CALIBRATON
12-BIT
DAC
16-BIT
-DAC
16-BIT
-DAC
16-BIT
PWM
16-BIT
PWM
BUF
DAC1
MUX
PWM0
PWM1
INTERNAL
BAND GAP
VREF
PLL2
OSC
20 MIPS 8052 BASED MCU WITH ADDITIONAL
PERIPHERALS
62 kBYTES FLASH/EE PROGRAM MEMORY
4 kBYTES FLASH/EE DATA MEMORY
2304 BYTES USER RAM
3 16 BIT TIMERS POWER SUPPLY MON
1 REAL TIME CLOCK WATCHDOG TIMER
4 PARALLEL
PORTS
UART, I2 C, AND SPI
SERIAL I/O
CREF
XTAL1 XTAL2
Figure 1.
GENERAL DESCRIPTION
The ADuC841/ADuC842/ADuC8431 are complete smart
transducer front ends, that integrates a high performance self-
calibrating multichannel ADC, a dual DAC, and an optimized
single-cycle 20 MHz 8-bit MCU (8051 instruction set compatible)
on a single chip.
The ADuC841 and ADuC842 are identical with the exception
of the clock oscillator circuit; the ADuC841 is clocked directly
from an external crystal up to 20 MHz whereas the ADuC842
uses a 32 kHz crystal with an on-chip PLL generating a
programmable core clock up to 16.78 MHz.
The ADuC843 is identical to the ADuC842 except that the
ADuC843 has no analog DAC outputs.
The microcontroller is an optimized 8052 core offering up to
20 MIPS peak performance. Three different memory options
are available offering up to 62 kBytes of nonvolatile Flash/EE
program memory. Four kBytes of nonvolatile Flash/EE data
memory, 256 bytes RAM, and 2 kBytes of extended RAM are
also integrated on-chip.
1 Protected by U.S. Patent No. 5,969,657.
(continued on page 15)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

No Preview Available !

ADuC841/ADuC842/ADuC843
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
General Description ......................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Absolute Maximum Ratings............................................................ 8 
ESD Caution.................................................................................. 8 
Pin Configurations and Function Descriptions ........................... 9 
Terminology .................................................................................... 19 
ADC Specifications .................................................................... 19 
DAC Specifications..................................................................... 19 
Typical Performance Characteristics ........................................... 20 
Functional Description .................................................................. 24 
8052 Instruction Set ................................................................... 24 
Other Single-Cycle Core Features ............................................ 26 
Memory Organization ............................................................... 27 
Special Function Registers (SFRs)............................................ 28 
Accumulator SFR (ACC)........................................................... 29 
Special Function Register Banks .............................................. 30 
ADC Circuit Information.......................................................... 31 
Calibrating the ADC .................................................................. 38 
Nonvolatile Flash/EE Memory ................................................. 39 
Using Flash/EE Data Memory .................................................. 42 
REVISION HISTORY
4/16—Rev. 0 to Rev. A
Added Patent Note, Note 1.............................................................. 1
Changes to Figure 3 and Table 3..................................................... 9
Changes to Figure 4........................................................................ 14
Added Table 4; Renumbered Sequentially .................................. 14
Data Sheet
User Interface to On-Chip Peripherals.................................... 46 
On-Chip PLL .............................................................................. 49 
Pulse-Width Modulator (PWM).............................................. 50 
Serial Peripheral Interface (SPI)............................................... 53 
I2C Compatible Interface........................................................... 56 
Dual Data Pointer....................................................................... 59 
Power Supply Monitor ............................................................... 60 
Watchdog Timer......................................................................... 61 
Time Interval Counter (TIC).................................................... 62 
8052 Compatible On-Chip Peripherals................................... 65 
Timer/Counter 0 and 1 Operating Modes.............................. 70 
Timer/Counter Operating Modes............................................ 72 
UART Serial Interface................................................................ 73 
SBUF ............................................................................................ 73 
Interrupt System ......................................................................... 78 
Hardware Design Considerations ............................................ 80 
Other Hardware Considerations .............................................. 84 
Development Tools .................................................................... 85 
QuickStart Development System ............................................. 85 
Timing Specifications, , .................................................................. 86 
Outline Dimensions ....................................................................... 94 
Ordering Guide .......................................................................... 95 
Changes to Using the DAC Section ............................................. 47
Updated Outline Dimensions....................................................... 94
Changes to Ordering Guide .......................................................... 95
11/03—Revision 0: Initial Version
Rev. A | Page 2 of 95

No Preview Available !

Data Sheet
ADuC841/ADuC842/ADuC843
SPECIFICATIONS1
Table 1. AVDD = DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; VREF = 2.5 V internal reference, fCORE = 16.78 MHz @ 5 V 8.38 MHz @ 3 V;
all specifications TA = TMIN to TMAX, unless otherwise noted
Parameter
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
DC ACCURACY2, 3
fSAMPLE = 120 kHz, see the Typical
Performance Characteristics for typical
performance at other values of fSAMPLE
Resolution
12 12 Bits
Integral Nonlinearity
±1
±1
LSB max
2.5 V internal reference
±0.3 ±0.3 LSB typ
Differential Nonlinearity
+1/–0.9
+1/–0.9
LSB max
2.5 V internal reference
±0.3 ±0.3 LSB typ
Integral Nonlinearity4
±2
±1.5
LSB max
1 V external reference
Differential Nonlinearity4
+1.5/–0.9 +1.5/–0.9 LSB max
1 V external reference
Code Distribution
1
1
LSB typ
ADC input is a dc voltage
CALIBRATED ENDPOINT ERRORS5, 6
Offset Error
±3 ±2 LSB max
Offset Error Match
±1 ±1 LSB typ
Gain Error
±3 ±2 LSB max
Gain Error Match
±1 ±1 LSB typ
DYNAMIC PERFORMANCE
fIN = 10 kHz sine wave
fSAMPLE = 120 kHz
Signal-to-Noise Ratio (SNR)7
71 71 dB typ
Total Harmonic Distortion (THD)
–85 –85 dB typ
Peak Harmonic or Spurious Noise –85 –85 dB typ
Channel-to-Channel Crosstalk8
–80 –80 dB typ
ANALOG INPUT
Input Voltage Range
Leakage Current
Input Capacitance
TEMPERATURE SENSOR9
Voltage Output at 25°C
Voltage TC
Accuracy
0 to VREF
±1
32
700
–1.4
±1.5
0 to VREF
±1
32
700
–1.4
±1.5
V
μA max
pF typ
mV typ
mV/°C typ
°C typ
Internal/External 2.5 V VREF
DAC CHANNEL SPECIFICATIONS
Internal Buffer Enabled
ADuC841/ADuC842 Only
DC ACCURACY10
Resolution
Relative Accuracy
Differential Nonlinearity11
Offset Error
Gain Error
Gain Error Mismatch
ANALOG OUTPUTS
Voltage Range_0
Voltage Range_1
Output Impedance
DAC load to AGND
RL = 10 kΩ, CL = 100 pF
12
±3
–1
±1/2
±50
±1
±1
0.5
0 to VREF
0 to VDD
0.5
12
±3
–1
±1/2
±50
±1
±1
0.5
0 to VREF
0 to VDD
0.5
Bits
LSB typ
LSB max
LSB typ
mV max
% max
% typ
% typ
V typ
V typ
Ω typ
Guaranteed 12-bit monotonic
VREF range
AVDD range
VREF range
% of full-scale on DAC1
DAC VREF = 2.5 V
DAC VREF = VDD
Rev. A | Page 3 of 95

No Preview Available !

ADuC841/ADuC842/ADuC843
Parameter
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
DAC CHANNEL SPECIFICATIONS12, 13
Internal Buffer Disabled ADuC841/ADuC842 Only
DC ACCURACY10
Resolution
Relative Accuracy
Differential Nonlinearity11
Offset Error
Gain Error
Gain Error Mismatch4
ANALOG OUTPUTS
Voltage Range_0
REFERENCE INPUT/OUTPUT REFERENCE OUTPUT14
Output Voltage (VREF)
Accuracy
Power Supply Rejection
Reference Temperature Coefficient
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUT15
Voltage Range (VREF) 4
Input Impedance
Input Leakage
POWER SUPPLY MONITOR (PSM)
DVDD Trip Point Selection Range
DVDD Power Supply Trip Point Accuracy
WATCHDOG TIMER (WDT) 4
Timeout Period
FLASH/EE MEMORY RELIABILITY CHARACTERISTICS16
Endurance17
Data Retention18
DIGITAL INPUTS
Input Leakage Current (Port 0, EA)
Logic 1 Input Current
(All Digital Inputs), SDATA, SCLOCK
Logic 0 Input Current (Ports 1, 2, 3) SDATA, SCLOCK
Logic 1 to Logic 0 Transition Current (Ports 2 and 3)
RESET
Data Sheet
VDD = 5 V VDD = 3 V Unit
15 15 μs typ
10 10 nV-sec typ
Test Conditions/Comments
Full-scale settling time to within
½ LSB of final value
1 LSB change at major carry
12
±3
–1
±1/2
±5
±0.5
0.5
0 to VREF
2.5
±10
65
±15
2
1
VDD
20
1
12
±3
–1
±1/2
±5
±0.5
0.5
0 to VREF
2.5
±10
67
±15
2
1
VDD
20
1
2.93
3.08
±2.5
0
2000
0
2000
100,000
100
100,000
100
±10 ±10
±1 ±1
±10
±1
–75
–40
–660
–400
±10
10
105
±10
±1
–25
–15
–250
–140
±10
5
35
Rev. A | Page 4 of 95
Bits
LSB typ
LSB max
LSB typ
mV max
% typ
% typ
Guaranteed 12-bit monotonic
VREF range
VREF range
% of full-scale on DAC1
V typ
DAC VREF = 2.5 V
V
mV Max
dB typ
ppm/°C typ
ms typ
Of VREF measured at the CREF pin
TA = 25°C
V min
V max
kΩ typ
μA max
Internal band gap deselected via
ADCCON1.6
V min
V max
% max
Two trip points selectable in this
range programmed via TPD1–0 in
PSMCON, 3 V part only
ms min
ms max
Nine timeout periods selectable in
this range
Cycles min
Years min
μA max
μA typ
VIN = 0 V or VDD
VIN = 0 V or VDD
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA min
μA max
VIN = VDD
VIN = VDD
VIL = 450 mV
VIL = 2 V
VIL = 2 V
VIN = 0 V
VIN = 5 V, 3 V Internal Pull Down
VIN = 5 V, 3 V Internal Pull Down

No Preview Available !

Data Sheet
Parameter
LOGIC INPUTS4
INPUT VOLTAGES
All Inputs Except SCLOCK, SDATA, RESET, and
XTAL1
VINL, Input Low Voltage
VINH, Input High Voltage
SDATA
VINL, Input Low Voltage
VINH, Input High Voltage
SCLOCK and RESET ONLY4
(Schmitt-Triggered Inputs)
VT+
VT–
VT+ – VT–
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
XTAL1 Input Capacitance
XTAL2 Output Capacitance
MCU CLOCK RATE
DIGITAL OUTPUTS
Output High Voltage (VOH)
VDD = 5 V
0.8
2.0
0.8
2.0
1.3
3.0
0.8
1.4
0.3
0.85
0.8
3.5
18
18
16.78
20
2.4
4
Output Low Voltage (VOL)
ALE, Ports 0 and 2
Port 3
SCLOCK/SDATA
Floating State Leakage Current4
STARTUP TIME
At Power-On
From Idle Mode
From Power-Down Mode
Wake-up with INT0 Interrupt
Wake-up with SPI/I2C Interrupt
Wake-up with External RESET
After External RESET in Normal Mode
After WDT Reset in Normal Mode
0.4
0.2
0.4
0.4
±10
±1
500
100
150
150
150
30
3
ADuC841/ADuC842/ADuC843
VDD = 3 V Unit
Test Conditions/Comments
0.4 V max
2.0 V min
0.8 V max
2.0 V min
0.95 V min
0.25 V max
0.4 V min
1.1 V max
0.3 V min
0.85 V max
0.4 V typ
2.5 V typ
18 pF typ
18 pF typ
8.38
MHz max
ADuC842/ADuC843 Only
8.38
MHz max
ADuC841 Only
V min
VDD = 4.5 V to 5.5 V
V typ
ISOURCE = 80 μA
2.4 V min VDD = 2.7 V to 3.3 V
2.6 V typ ISOURCE = 20 μA
0.4
V max
ISINK = 1.6 mA
0.2 V typ ISINK = 1.6 mA
0.4
V max
ISINK = 4 mA
0.4
V max
ISINK = 8 mA, I2C Enabled
±10 μA max
±1 μA typ
At any core CLK
500 ms typ
100 μs typ
400 μs typ
400 μs typ
400 μs typ
30 ms typ
3
ms typ
Controlled via WDCON SFR
Rev. A | Page 5 of 95