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DATASHEET
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
932SQ426
General Description
Features/Benefits
The 932SQ426 is a CK420BQ derivative supporting
Separate Reference no Spread (SRnS) PCIe clocking
architectures. It uses a 25MHz crystal for maximum
performance and has 100MHz outputs tuned for
non-spreading applications to provide the most open eye
diagram on PCIe links.
Non-spread 100MHz outputs/ Supports SRnS PCIe
architectures
64-pin TSSOP and VFQFPN packages; maximum space
savings
Key Specifications
Recommended Application
CK420BQ for SRnS applications
Output Features
11 - HCSL 100MHz outputs for SRnS
4 - NS_SAS/SRC outputs
4 - CPU outputs
3 - SRC outputs
1 - HCSL DOT96 output
1 - 3.3V 48M output
5 - 3.3V PCI outputs
1 - 3.3V 14.318M output
Cycle to cycle jitter: CPU/SRC/NS_SRC/NS_SAS < 50ps
Phase jitter: PCIe Gen2 <3ps rms
Phase jitter: PCIe Gen3 <1ps rms
Phase jitter: QPI 9.6GB/s <0.2ps rms
Phase jitter: NS-SAS <0.4ps rms using raw phase data
Phase jitter: NS-SAS <1.3ps rms using Clk Jit Tool 1.6.4
Block Diagram
X1_25
X2
Low Drift non-SS
PLL
<500ps LTJ
Non-SS PLL
CPU(3:0)
SRC(2:0)
/3 PCI(4:0)
NS_SAS(1:0)
NS_SRC(1:0)
DOT96
48M
Test_Sel
Test_Mode
CKPWRGD#/PD
SMBDAT
SMBCLK
Logic
14.31818MHz
Non-SS PLL
REF14M
IREF
IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
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932SQ426
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
Pin Configuration (TSSOP)
SMBCLK 1
64 SMBDAT
GND14 2
63 VDDCPU
AVDD14 3
62 CPU3T
VDD14 4
vREF14_3x/TEST_SEL 5
61 CPU3C
60 CPU2T
GND14 6
59 CPU2C
GNDXTAL 7
58 GNDCPU
X1_25 8
57 VDDCPU
X2_25 9
56 CPU1T
VDDXTAL 10
55 CPU1C
GN DPCI 11
54 CPU0T
VD DPCI 12
53 CPU0C
PCI4_2x 13
52 GNDNS
PCI3_2x 14
51 AVDD_NS_SAS
PCI2_2x 15
50 NS_SAS1T
PCI1_2x 16
49 NS_SAS1C
PCI0_2x 17
48 NS_SAS0T
GN DPCI 18
47 NS_SAS0C
VD DPCI 19
46 GNDNS
VDD48 20
45 VDDNS
48M_2x 21
44 NS_SRC1T
GND48 22
43 NS_SRC1C
GND96 23
42 NS_SRC0T
DOT96T 24
41 NS_SRC0C
DOT96C 25
40 IREF
AVDD96 26
39 GNDSRC
TEST_MODE 27
38 AVDD_SRC
CKPWR GD#/PD 28
37 VDDSRC
VD DSRC 29
36 SRC2T
SRC0T 30
35 SRC2C
SRC0C 31
34 SRC1T
GN DSRC 32
33 SRC1C
64-TSSOP
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldown
932SQ426 Functionality
CPU, SRC,
NS_SAS,
NS _SR C
100
PCI
33.3 3
REF
14.3 18
DOT96
9 6.00
USB
48.00 MHz
Power Group Pin Numbers
QFN
TSSOP
Description
VDD GND VDD GND
57 56
3
2 14MHz PLL Analog
58 60 4
6 REF14M Output and Logic
64 61 10
7 25MHz XTAL
2,9 1,8 12, 19 11,18 PCI Outputs and Logic
10 12 20
22 48MHz Output and Logic
16 13 26
23 96MHz PLL Analog, Output and Logic
19,27,28 22 29,37,38 32,39 SRC Outputs and Logic
35 36 45
46 Non-Spreading Differential Outputs & Logic
41 42 51
52 NS-SAS/SRC PLL Analog
47,53 48 57,63 58 CPU Outputs and Logic
932SQ426 Power Down Functionality
CKP WRG D#/ PD
1
0
D ifferential
Outputs
S ingl e-
ende d
Outputs
HI-Z1
Low
Running
Single
ended
Outputs
w/La tc h
Lo w2
1. Hi-Z on the differential outputs w ill result in both True
and Complement being low due to the termination
2. These outputs are Hi-Z after VDD is applied and before
the first assertion of CKPWR GD#.
IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
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932SQ426
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
Pin Descriptions (TSSOP)
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PIN NAME
TYPE
DESCRIPTION
SMBCLK
IN Clock pin of SMBUS circuitry, 5V tolerant
GND14
PWR Ground pin for 14MHz output and logic.
AVDD14
PWR Analog power pin for 14MHz PLL
VDD14
PWR Power pin for 14MHz output and logic
vREF14_3x/TEST_SEL I/O 14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode.
Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down.
GND14
PWR Ground pin for 14MHz output and logic.
GNDXTAL
PWR Ground pin for Crystal Oscillator.
X1_25
IN Crystal input, Nominally 25.00MHz.
X2_25
OUT Crystal output, Nominally 25.00MHz.
VDDXTAL
PWR 3.3V power for the crystal oscillator.
GNDPCI
PWR Ground pin for PCI outputs and logic.
VDDPCI
PWR 3.3V power for the PCI outputs and logic
PCI4_2x
OUT 3.3V PCI clock output
PCI3_2x
OUT 3.3V PCI clock output
PCI2_2x
OUT 3.3V PCI clock output
PCI1_2x
OUT 3.3V PCI clock output
PCI0_2x
OUT 3.3V PCI clock output
GNDPCI
PWR Ground pin for PCI outputs and logic.
VDDPCI
PWR 3.3V power for the PCI outputs and logic
VDD48
PWR 3.3V power for the 48MHz output and logic
48M_2x
OUT 3.3V 48MHz output
GND48
PWR Ground pin for 48MHz output and logic.
GND96
PWR Ground pin for DOT96 output and logic.
True clock of differential 96MHz output. These are current mode outputs and external series resistors
DOT96T
OUT and shunt resistors are required for termination. See Test Loads and Recommended Terminations for
specific values.
Complementary clock of differential 96MHz output. These are current mode outputs and external series
DOT96C
OUT resistors and shunt resistors are required for termination. See Test Loads and Recommended
Terminations for specific values.
AVDD96
PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
TEST_MODE
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is
CKPWRGD#/PD
IN an asynchronous active high input pin used to put the device into a low power state. The internal clocks
and PLLs are stopped.
VDDSRC
PWR 3.3V power for the SRC outputs and logic
True clock of differential SRC output. These are current mode outputs and external series resistors and
SRC0T
OUT shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific
values.
Complementary clock of differential SRC output. These are current mode outputs and external series
SRC0C
OUT resistors and shunt resistors are required for termination. See Test Loads and Recommended
Terminations for specific values.
GNDSRC
PWR Ground pin for SRC outputs and logic.
Complementary clock of differential SRC output. These are current mode outputs and external series
SRC1C
OUT resistors and shunt resistors are required for termination. See Test Loads and Recommended
Terminations for specific values.
True clock of differential SRC output. These are current mode outputs and external series resistors and
SRC1T
OUT shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific
values.
Complementary clock of differential SRC output. These are current mode outputs and external series
SRC2C
OUT resistors and shunt resistors are required for termination. See Test Loads and Recommended
Terminations for specific values.
True clock of differential SRC output. These are current mode outputs and external series resistors and
SRC2T
OUT shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific
values.
VDDSRC
PWR 3.3V power for the SRC outputs and logic
AVDD_SRC
PWR 3.3V power for the SRC PLL analog circuits
GNDSRC
PWR Ground pin for SRC outputs and logic.
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a
IREF
OUT fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the
standard value.
IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING
3
932SQ426
REV C 022916