Complete 12-Bit, 65 MSPS
Signal-to-Noise Ratio: 69 dB @ fIN = 31 MHz
Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHz
Intermodulation Distortion of –75 dBFS @ fIN = 140 MHz
ENOB = 11.1 @ fIN = 10 MHz
Low-Power Dissipation: 475 mW
No Missing Codes Guaranteed
Differential Nonlinearity Error: ؎0.6 LSB
Integral Nonlinearity Error: ؎0.6 LSB
Clock Duty Cycle Stabilizer
Patented On-Chip Sample-and-Hold with
Full Power Bandwidth of 750 MHz
Straight Binary or Two’s Complement Output Data
28-Lead SSOP, 48-Lead LQFP
Single 5 V Analog Supply, 3 V/5 V Driver Supply
Pin-Compatible to AD9220, AD9221, AD9223,
FUNCTIONAL BLOCK DIAGRAM
DUTY CYCLE STABILIZER
The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS
analog-to-digital converter with an on-chip, high-performance
sample-and-hold amplifier and voltage reference. The AD9226
uses a multistage differential pipelined architecture with a pat-
ented input stage and output error correction logic to provide
12-bit accuracy at 65 MSPS data rates. There are no missing
codes over the full operating temperature range (guaranteed).
The input of the AD9226 allows for easy interfacing to both
imaging and communications systems. With a truly differential
input structure, the user can select a variety of input ranges and
offsets including single-ended applications.
The sample-and-hold amplifier (SHA) is well suited for IF
undersampling schemes such as in single-channel communi-
cation applications with input frequencies up to and well
beyond Nyquist frequencies.
The AD9226 has an on-board programmable reference. For sys-
tem design flexibility, an external reference can also be chosen.
A single clock input is used to control all internal conversion
cycles. An out-of-range signal indicates an overflow condition
that can be used with the most significant bit to determine low
or high overflow.
The AD9226 has two important mode functions. One will set
the data format to binary or two’s complement. The second will
make the ADC immune to clock duty cycle variations.
IF Sampling—The patented SHA input can be configured for
either single-ended or differential inputs. It will maintain out-
standing AC performance up to input frequencies of 300 MHz.
Low Power—The AD9226 at 475 mW consumes a fraction of
the power presently available in existing, high-speed monolithic
Out of Range (OTR)—The OTR output bit indicates when
the input signal is beyond the AD9226’s input range.
Single Supply—The AD9226 uses a single 5 V power supply
simplifying system power supply design. It also features a sepa-
rate digital output driver supply line to accommodate 3 V and
5 V logic families.
Pin Compatibility—The AD9226 is similar to the AD9220,
AD9221, AD9223, AD9224, and AD9225 ADCs.
Clock Duty Cycle Stabilizer—Makes conversion immune to
varying clock pulsewidths.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2001