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a
Complete 12-Bit, 65 MSPS
ADC Converter
AD9226
FEATURES
Signal-to-Noise Ratio: 69 dB @ fIN = 31 MHz
Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHz
Intermodulation Distortion of –75 dBFS @ fIN = 140 MHz
ENOB = 11.1 @ fIN = 10 MHz
Low-Power Dissipation: 475 mW
No Missing Codes Guaranteed
Differential Nonlinearity Error: ؎0.6 LSB
Integral Nonlinearity Error: ؎0.6 LSB
Clock Duty Cycle Stabilizer
Patented On-Chip Sample-and-Hold with
Full Power Bandwidth of 750 MHz
Straight Binary or Two’s Complement Output Data
28-Lead SSOP, 48-Lead LQFP
Single 5 V Analog Supply, 3 V/5 V Driver Supply
Pin-Compatible to AD9220, AD9221, AD9223,
AD9224, AD9225
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD
DRVDD
VINA
VINB
CAPT
CAPB
VREF
SENSE
DUTY CYCLE STABILIZER
SHA
MDAC1
8-STAGE
1-1/2-BIT PIPELINE
A/D
A/D 4
16
3
CALIBRATION
ROM
CORRECTION LOGIC
12
OUTPUT BUFFERS
REF 1V
SELECT
MODE
SELECT
AD9226
REFCOM MODE
AVSS DRVSS
OTR
BIT 1
(MSB)
BIT 12
(LSB)
PRODUCT DESCRIPTION
The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS
analog-to-digital converter with an on-chip, high-performance
sample-and-hold amplifier and voltage reference. The AD9226
uses a multistage differential pipelined architecture with a pat-
ented input stage and output error correction logic to provide
12-bit accuracy at 65 MSPS data rates. There are no missing
codes over the full operating temperature range (guaranteed).
The input of the AD9226 allows for easy interfacing to both
imaging and communications systems. With a truly differential
input structure, the user can select a variety of input ranges and
offsets including single-ended applications.
The sample-and-hold amplifier (SHA) is well suited for IF
undersampling schemes such as in single-channel communi-
cation applications with input frequencies up to and well
beyond Nyquist frequencies.
The AD9226 has an on-board programmable reference. For sys-
tem design flexibility, an external reference can also be chosen.
A single clock input is used to control all internal conversion
cycles. An out-of-range signal indicates an overflow condition
that can be used with the most significant bit to determine low
or high overflow.
The AD9226 has two important mode functions. One will set
the data format to binary or two’s complement. The second will
make the ADC immune to clock duty cycle variations.
PRODUCT HIGHLIGHTS
IF Sampling—The patented SHA input can be configured for
either single-ended or differential inputs. It will maintain out-
standing AC performance up to input frequencies of 300 MHz.
Low Power—The AD9226 at 475 mW consumes a fraction of
the power presently available in existing, high-speed monolithic
solutions.
Out of Range (OTR)—The OTR output bit indicates when
the input signal is beyond the AD9226’s input range.
Single Supply—The AD9226 uses a single 5 V power supply
simplifying system power supply design. It also features a sepa-
rate digital output driver supply line to accommodate 3 V and
5 V logic families.
Pin Compatibility—The AD9226 is similar to the AD9220,
AD9221, AD9223, AD9224, and AD9225 ADCs.
Clock Duty Cycle Stabilizer—Makes conversion immune to
varying clock pulsewidths.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001

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AD9226* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Documentation
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-302: Exploit Digital Advantages in an SSB Receiver
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-348: Avoiding Passive-Component Pitfalls
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-742: Frequency Domain Response of Switched-
Capacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9226: Complete 12-Bit, 65 MSPS ADC Converter Data
Sheet
User Guides
• UG-173: High Speed ADC USB FIFO Evaluation Kit
(HSC-ADC-EVALB-DCZ)
Tools and Simulations
• Visual Analog
Reference Materials
Technical Articles
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• DNL and Some of its Effects on Converter Performance
• MS-2210: Designing Power Supplies for High Speed ADC
Design Resources
• AD9226 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9226 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
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number
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AD9226–SPECIFICATIONS
DC SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, Differential inputs, TMIN to TMAX unless otherwise
noted.)
Parameter
Temp Test Level
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes Guaranteed
Zero Error
Gain Error
Full
25°C
Full
25°C
Full
Full
25°C
25°C
Full
V
I
V
I
I
V
I
I
V
TEMPERATURE DRIFT
Zero Error
Gain Error1
Gain Error2
Full V
Full V
Full V
POWER SUPPLY REJECTION
AVDD (5 V ± 0.25 V)
Full
25°C
V
I
INPUT REFERRED NOISE
VREF = 1.0 V
VREF = 2.0 V
Full V
Full V
ANALOG INPUT
Input Span (VREF = 1 V)
(VREF = 2 V)
Input (VINA or VINB) Range
Input Capacitance
Full V
Full V
Full IV
Full V
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2.0 V Mode)
Output Voltage Tolerance (2.0 V Mode)
Output Current (Available for External Loads)
Load Regulation3
Full
25°C
Full
25°C
Full
Full
25°C
V
I
V
I
V
V
I
REFERENCE INPUT RESISTANCE
Full V
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD4
IDRVDD5
POWER CONSUMPTION4, 5
Full
Full
Full
25°C
Full
25°C
Full
25°C
V
V
V
I
V
I
V
I
NOTES
1Includes internal voltage reference error.
2Excludes internal voltage reference error.
3Load regulation with 1 mA load current (in addition to that required by the AD9226).
4AVDD = 5 V
5DRVDD = 3 V
Specifications subject to change without notice.
Min Typ Max
12
± 0.6
± 1.6
± 0.6
± 1.0
12
± 0.3
± 1.4
± 2.0
± 0.6
±2
± 26
± 0.4
± 0.05
± 0.4
0.5
0.25
1
2
0 AVDD
7
1.0
± 15
2.0
± 29
1.0
0.7
1.5
5
4.75 5
2.85
5.25
5.25
86
90.5
14.6
16.5
475
500
Unit
Bits
LSB
LSB
LSB
LSB
Bits
% FSR
% FSR
% FSR
% FSR
ppm/°C
ppm/°C
ppm/°C
% FSR
% FSR
LSB rms
LSB rms
V p-p
V p-p
V
pF
V
mV
V
mV
mA
mV
mV
k
V (± 5% AVDD Operating)
V (± 5% DRVDD Operating)
mA (2 V External VREF)
mA (2 V External VREF)
mA (2 V External VREF)
mA (2 V External VREF)
mW (2 V External VREF)
–2– REV. B

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AD9226
DIGITAL SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)
Parameters
LOGIC INPUTS (Clock, DFS1, Duty Cycle1, and
Output Enable1)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current (VIN = AVDD)
Low-Level Input Current (VIN = 0 V)
Input Capacitance
Output Enable1
Temp
Full
Full
Full
Full
Full
Full
LOGIC OUTPUTS (With DRVDD = 5 V)
High-Level Output Voltage (IOH = 50 µA)
High-Level Output Voltage (IOH = 0.5 mA)
Low-Level Output Voltage (IOL = 1.6 mA)
Low-Level Output Voltage (IOL = 50 µA)
Output Capacitance
Full
Full
Full
Full
Test Level Min
Typ
IV 2.4
IV
IV –10
IV –10
V5
IV DRVDD 0.5
2
IV 4.5
IV 2.4
IV
IV
5
Max
Unit
0.8
+10
+10
DRVDD + 0.5
2
V
V
µA
µA
pF
V
V
V
0.4 V
0.1 V
pF
LOGIC OUTPUTS (With DRVDD = 3 V)
High-Level Output Voltage (IOH = 50 µA)
High-Level Output Voltage (IOH = 0.5 mA)
Low-Level Output Voltage (IOL = 1.6 mA)
Low-Level Output Voltage (IOL = 50 µA)
NOTES
1LQFP package.
Specifications subject to change without notice.
Full IV
Full IV
Full IV
Full IV
2.95
2.80
V
V
0.4 V
0.05 V
SWITCHING SPECIFICATIONS (TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)
Parameters
Temp
Test Level Min
Typ
Max Conversion Rate
Clock Period1
CLOCK Pulsewidth High2
CLOCK Pulsewidth Low2
Output Delay
Pipeline Delay (Latency)
Output Enable Delay3
Full VI
Full V
Full V
Full V
Full V
Full V
Full V
65
15.38
3
3
3.5
7
15
NOTES
1The clock period may be extended to 10 µs without degradation in specified performance @ 25°C.
2When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.
3LQFP package.
Specifications subject to change without notice.
Max Unit
MHz
ns
ns
ns
7 ns
Clock Cycles
ns
ANALOG
INPUT
n
n+1 n+2
n+3
n+4
n+5
n+7
n+6
n+8
REV. B
CLOCK
DATA n–8 n–7 n–6 n–5
OUT
n–4 n–3 n–2
n–1 n n+1
Figure 1. Timing Diagram
TOD = 7.0 MAX
3.5 MIN
–3–

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AD9226–SPECIFICATIONS
AC SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted.)
Parameter
Temp
Test Level
Min Typ Max
Unit
SIGNAL-TO-NOISE RATIO
fIN = 2.5 MHz
fIN = 15 MHz
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
SIGNAL-TO-NOISE RATIO AND DISTORTION
fIN = 2.5 MHz
fIN = 15 MHz
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
TOTAL HARMONIC DISTORTION
fIN = 2.5 MHz
fIN = 15 MHz
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
SECOND AND THIRD HARMONIC DISTORTION
fIN = 2.5 MHz
fIN = 15 MHz
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
SPURIOUS FREE DYNAMIC RANGE
fIN = 2.5 MHz
fIN = 15 MHz
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
ANALOG INPUT BANDWIDTH
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
25°C
V
I
V
I
V
V
V
V
I
V
I
V
V
V
V
I
V
I
V
V
V
V
I
V
I
V
V
V
V
I
V
I
V
V
V
V
68.9
68
68.4
67.4
68
68
65
68.8
67.9
68.3
67.3
67
67
60
84
82.3
68
68
61
77.0
76.0
86.5
86.7
83
82
75
78
76
86.4
78
85.5
76
82
81
60
750
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
NOTES
11.0 V Reference and Input Span
Specifications subject to change without notice.
–4– REV. B