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Data Sheet
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.55 GHz to 2.95 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
6 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
4 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
64-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9516-01 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz
to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9516-0 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
14-Output Clock Generator with
Integrated 2.8 GHz VCO
AD9516-0
FUNCTIONAL BLOCK DIAGRAM
CP LF
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
LVPECL
DIV/Φ
LVPECL
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
LVPECL
Δt
Δt
LVDS/CMOS
Δt
Δt
LVDS/CMOS
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
AD9516-0
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Figure 1.
The AD9516-0 features six LVPECL outputs (in three pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The AD9516-0 is available in a 64-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9516-0 is specified for operation over the industrial
range of −40°C to +85°C.
1 AD9516 is used throughout to refer to all the members of the AD9516
family. However, when AD9516-0 is used, it refers to that specific member
of the AD9516 family.
Rev. C
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AD9516-0* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Evaluation Kits
• AD9516-0 Evaluation Board
Documentation
Application Notes
• AN-0974: Multicarrier TD-SCMA Feasibility
• AN-0983: Introduction to Zero-Delay Clock Timing
Techniques
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-769: Generating Multiple Clock Outputs from the
AD9540
• AN-823: Direct Digital Synthesizers in Clocking
Applications Time
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-837: DDS-Based Clock Jitter Performance vs. DAC
Reconstruction Filter Performance
• AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
• AN-927: Determining if a Spur is Related to the DDS/DAC
or to Some Other Source (For Example, Switching
Supplies)
• AN-939: Super-Nyquist Operation of the AD9912 Yields a
High RF Output Signal
Data Sheet
• AD9516-0: 14-Output Clock Generator with Integrated 2.8
GHz VCO Data Sheet
User Guides
• UG-075: AD9516-x, AD9517-x, and AD9518-x Evaluation
Board User Guide
• UG-093: Evaluation Board User Guide for the Dual,
Continuous Time Sigma-Delta Modulator
Tools and Simulations
• ADIsimCLK Design and Evaluation Software
• AD9516 IBIS Models
Reference Designs
• CN0243
Reference Materials
Product Selection Guide
• RF Source Booklet
Technical Articles
• ADI Buys Korean Mobile TV Chip Maker
• Clock Requirements For Data Converters
• Design A Clock-Distribution Strategy With Confidence
• Improved DDS Devices Enable Advanced Comm Systems
• Low-power direct digital synthesizer cores enable high level
of integration
• Speedy A/Ds Demand Stable Clocks
• Understand the Effects of Clock Jitter and Phase Noise on
Sampled Systems
Design Resources
• AD9516-0 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9516-0 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
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AD9516-0
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs ............................................................................... 6
Timing Characteristics ................................................................ 7
Clock Output Additive Phase Noise (Distribution Only; VCO
Divider Not Used) ........................................................................ 8
Clock Output Absolute Phase Noise (Internal VCO Used).... 9
Clock Output Absolute Time Jitter (Clock Generation Using
Internal VCO)............................................................................. 10
Clock Output Absolute Time Jitter (Clock Cleanup Using
Internal VCO)............................................................................. 10
Clock Output Absolute Time Jitter (Clock Generation Using
External VCXO) ......................................................................... 10
Clock Output Additive Time Jitter (VCO Divider Not Used)
....................................................................................................... 11
Clock Output Additive Time Jitter (VCO Divider Used) ..... 11
Delay Block Additive Time Jitter.............................................. 12
Serial Control Port ..................................................................... 12
PD, RESET, and SYNC Pins ..................................................... 13
LD, STATUS, and REFMON Pins............................................ 13
Power Dissipation....................................................................... 14
Timing Diagrams............................................................................ 15
Absolute Maximum Ratings.......................................................... 16
Data Sheet
Thermal Resistance .................................................................... 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 19
Terminology .................................................................................... 25
Detailed Block Diagram ................................................................ 26
Theory of Operation ...................................................................... 27
Operational Configurations...................................................... 27
Digital Lock Detect (DLD) ....................................................... 36
Clock Distribution ..................................................................... 40
Reset Modes ................................................................................ 48
Power-Down Modes .................................................................. 49
Serial Control Port ......................................................................... 50
Serial Control Port Pin Descriptions ....................................... 50
General Operation of Serial Control Port............................... 50
The Instruction Word (16 Bits) ................................................ 51
MSB/LSB First Transfers ........................................................... 51
Thermal Performance.................................................................... 54
Register Map Overview ................................................................. 55
Register Map Descriptions ............................................................ 59
Applications Information .............................................................. 77
Frequency Planning Using the AD9516.................................. 77
Using the AD9516 Outputs for ADC Clock Applications.... 77
LVPECL Clock Distribution ..................................................... 78
LVDS Clock Distribution .......................................................... 78
CMOS Clock Distribution ........................................................ 79
Outline Dimensions ....................................................................... 80
Ordering Guide .......................................................................... 80
Rev. C | Page 2 of 80

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Data Sheet
REVISION HISTORY
2/13—Rev. B to Rev. C
Changes to Register 0x140 to Register 0x143 Default Values;
Table 52.............................................................................................56
Changes to Register 0x140 to Register 0x143 Default Values;
Table 57.............................................................................................71
Updated Outline Dimensions........................................................80
1/12—Rev. A to Rev. B
Changes to 0x232 Description Column, Table 62 ......................76
12/10—Rev. 0 to Rev. A
Changes to Features, Applications, and General Description..... 1
Change to CPRSET Pin Resistor Parameter in Table 1 ................ 4
Change to P = 2 DM (2/3) Parameter in Table 2 .......................... 5
Changes to Table 4 ............................................................................ 6
Changes to VCP Supply Parameter in Table 17.............................14
Change to θJA Value and Endnote in Table 19 .............................16
Added Exposed Paddle Notation to Figure 6; Changes to
Table 20.............................................................................................17
Added Figure 41; Renumbered Sequentially ...............................24
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 22..........27
Changes to Table 24 ........................................................................29
Change to Configuration and Register Settings Section............31
Change to Phase Frequency Detector (PFD) Section ................32
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections .........33
Change to Figure 47; Added Figure 48.........................................33
AD9516-0
Changes to Reference Switchover and VCXO/VCO
Feedback Divider N—P, A, B, R Sections .................................... 34
Changes to Table 28 ........................................................................ 35
Change to Holdover Section.......................................................... 37
Changes to VCO Calibration Section........................................... 39
Changes to Clock Distribution Section........................................ 40
Added Endnote to Table 34 ........................................................... 41
Changes to Channel Dividers—LVDS/CMOS Outputs
Section; Added Endnote to Table 39 ............................................ 43
Changes to Write Section............................................................... 50
Change to the Instruction Word (16 Bits) Section ..................... 51
Change to Figure 65........................................................................ 52
Added Thermal Performance Section.......................................... 54
Changes to Register Address 0x003 in Table 52.......................... 55
Changes to Table 53 ........................................................................ 59
Changes to Table 54 ........................................................................ 60
Changes to Table 55 ........................................................................ 66
Changes to Table 56 ........................................................................ 68
Changes to Table 57 ........................................................................ 71
Changes to Table 58 ........................................................................ 73
Changes to Table 59 ........................................................................ 74
Changes to Table 60 and Table 61 ................................................. 76
Added Frequency Planning Using the AD9516 Section............ 77
Changes to Figure 71 and Figure 73; Added Figure 72.............. 78
Changes to LVPECL Clock Distribution and LVDS Clock
Distribution Sections ...................................................................... 78
Updated Outline Dimensions........................................................80
4/07—Revision 0: Initial Version
Rev. C | Page 3 of 80

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AD9516-0
Data Sheet
SPECIFICATIONS
Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_LVPECL
VCP
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
Min
3.135
2.375
VS
2.7
Typ
3.3
4.12
5.1
Max
3.465
VS
5.25
10
Unit
V
V
V
kΩ
kΩ
220 nF
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);
actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect
to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Frequency Pushing (Open-Loop)
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
Min Typ Max Unit Test Conditions/Comments
2550
0.5
50
1
−105
−123
2950
VCP
0.5
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
See Figure 15
See Figure 10
VCP ≤ VS when using internal VCO; outside of this range, the CP
spurs may increase due to CP up/down mismatch
f = 2800 MHz
f = 2800 MHz
0
250
1.35 1.60
1.30 1.50
4.0 4.8
4.4 5.3
20
0
0.8
2.0
−100
2
250
1.75
1.60
5.9
6.4
250
250
0.8
+100
MHz
mV p-p
V
V
kΩ
kΩ
MHz
MHz
V p-p
V
V
µA
pF
Differential mode (can accommodate single-ended input by
ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled; be careful
to match VCM (self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew rate; see
Figure 14
Self-bias voltage of REFIN1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/µs
Slew rate > 50 V/µs; CMOS levels
Should not exceed VS p-p
Each pin, REFIN/REFIN (REF1/REF2)
100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns
45 MHz Antibacklash pulse width = 6.0 ns
1.3 ns Register 0x017[1:0] = 01b
2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
6.0 ns Register 0x017[1:0] = 10b
Rev. C | Page 4 of 80