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Data Sheet
12 LVDS/24 CMOS Output Clock Generator
with Integrated 1.6 GHz VCO
AD9522-4
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip voltage controlled oscillator (VCO) tunes from
1.4 GHz to 1.8 GHz
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVPECL, or LVDS references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Revertive automatic and manual reference switchover/
holdover modes
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 800 MHz LVDS outputs divided into 4 groups
Each group of 3 has a 1-to-32 divider with phase delay
Additive output jitter as low as 242 fs rms
Channel-to-channel skew grouped outputs <60 ps
Each LVDS output can be configured as 2 CMOS outputs
(for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9522-41 provides a multioutput clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to
1.8 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
FUNCTIONAL BLOCK DIAGRAM
CP LF
OPTIONAL
REFIN
REFIN
CLK
REF1
REF2
DIVIDER
AND MUXES
DIV/Φ
VCO
STATUS
MONITOR
ZERO
DELAY
LVDS/
CMOS
DIV/Φ
DIV/Φ
DIV/Φ
SPI/I2C CONTROL
PORT AND
EEPROM
DIGITAL LOGIC
AD9522
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
Figure 1.
The AD9522 serial interface supports both SPI and I2C® ports.
An in-package EEPROM can be programmed through the
serial interface and store user-defined register settings for
power-up and chip reset.
The AD9522 features 12 LVDS outputs in four groups. Any of
the 800 MHz LVDS outputs can be reconfigured as two 250 MHz
CMOS outputs.
Each group of outputs has a divider that allows both the divide
ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9522 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage up to 5.5 V.
The AD9522 is specified for operation over the standard industrial
range of −40°C to +85°C.
The AD9520-4 is an equivalent device to the AD9522-4 featuring
LVPECL/CMOS drivers instead of LVDS/CMOS drivers.
1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-4 is used, it is referring to that specific
member of the AD9522 family.
Rev. A
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AD9522-4* Product Page Quick Links
Last Content Update: 11/01/2016
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Evaluation Kits
• AD9522-4 Evaluation Board
Documentation
Application Notes
• AN-0983: Introduction to Zero-Delay Clock Timing
Techniques
Data Sheet
• AD9522-4: 12 LVDS/24 CMOS Output Clock Generator
with Integrated 1.6 GHz VCO Data Sheet
User Guides
• Evaluation Software Documentation
Software and Systems Requirements
• Evaluation Software Tools
Tools and Simulations
• ADIsimCLK Design and Evaluation Software
• AD9522-x IBIS Models
Reference Materials
Product Selection Guide
• RF Source Booklet
Design Resources
• AD9522-4 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
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AD9522-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 4
Specifications..................................................................................... 5
Power Supply Requirements ....................................................... 5
PLL Characteristics ...................................................................... 5
Clock Inputs .................................................................................. 8
Clock Outputs ............................................................................... 8
Timing Characteristics ................................................................ 9
Timing Diagrams ..................................................................... 9
Clock Output Additive Phase Noise (Distribution Only; VCO
Divider Not Used) ...................................................................... 10
Clock Output Absolute Phase Noise (Internal VCO Used).. 11
Clock Output Absolute Time Jitter (Clock Generation Using
Internal VCO)............................................................................. 11
Clock Output Absolute Time Jitter (Clock Cleanup Using
Internal VCO)............................................................................. 11
Clock Output Absolute Time Jitter (Clock Generation Using
External VCXO) ......................................................................... 12
Clock Output Additive Time Jitter (VCO Divider Not Used)
....................................................................................................... 12
Clock Output Additive Time Jitter (VCO Divider Used) ..... 13
Serial Control Port—SPI Mode ................................................ 13
Serial Control Port—I²C Mode ................................................ 14
PD, SYNC, and RESET Pins ..................................................... 15
Serial Port Setup Pins: SP1, SP0 ............................................... 15
LD, STATUS, and REFMON Pins............................................ 15
Power Dissipation....................................................................... 16
Absolute Maximum Ratings.......................................................... 17
Thermal Resistance .................................................................... 17
ESD Caution................................................................................ 17
Pin Configuration and Function Descriptions........................... 18
Typical Performance Characteristics ........................................... 21
Test Circuits..................................................................................... 26
Terminology .................................................................................... 27
Detailed Block Diagram ................................................................ 28
Theory of Operation ...................................................................... 29
Operational Configurations...................................................... 29
Mode 0: Internal VCO and Clock Distribution ................. 29
Mode 1: Clock Distribution or External VCO <1600 MHz
.................................................................................................. 31
Mode 2: High Frequency Clock Distribution—CLK or
External VCO >1600 MHz ................................................... 33
Phase-Locked Loop (PLL) .................................................... 35
Configuration of the PLL ...................................................... 35
Phase Frequency Detector (PFD) ........................................ 35
Charge Pump (CP)................................................................. 35
On-Chip VCO ........................................................................ 36
PLL External Loop Filter....................................................... 36
PLL Reference Inputs............................................................. 36
Reference Switchover............................................................. 37
Reference Divider R ............................................................... 37
VCO/VCXO Feedback Divider N: P, A, B .......................... 37
Digital Lock Detect (DLD) ................................................... 39
Analog Lock Detect (ALD)................................................... 39
Current Source Digital Lock Detect (CSDLD) .................. 39
External VCXO/VCO Clock Input (CLK/CLK)................ 40
Holdover.................................................................................. 40
External/Manual Holdover Mode........................................ 40
Automatic/Internal Holdover Mode.................................... 40
Frequency Status Monitors ................................................... 42
VCO Calibration .................................................................... 42
Zero Delay Operation................................................................ 45
Internal Zero Delay Mode..................................................... 45
External Zero Delay Mode.................................................... 45
Clock Distribution ..................................................................... 46
Operation Modes ................................................................... 46
Clock Frequency Division..................................................... 47
VCO Divider........................................................................... 47
Channel Dividers ................................................................... 47
Synchronizing the Outputs—SYNC Function ................... 49
LVDS Output Drivers ............................................................ 50
CMOS Output Drivers .......................................................... 51
Reset Modes ................................................................................ 51
Power-On Reset...................................................................... 51
Hardware Reset via the RESET Pin ..................................... 51
Soft Reset via the Serial Port................................................. 51
Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via
the Serial Port ......................................................................... 51
Rev. A | Page 2 of 84

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Data Sheet
Power-Down Modes ...................................................................51
Chip Power-Down via PD .....................................................51
PLL Power-Down....................................................................52
Distribution Power-Down .....................................................52
Individual Clock Output Power-Down................................52
Individual Clock Channel Power-Down .............................52
Serial Control Port ..........................................................................53
SPI/I²C Port Selection ................................................................53
I²C Serial Port Operation...........................................................53
I2C Bus Characteristics...........................................................53
Data Transfer Process .............................................................54
Data Transfer Format .............................................................55
I²C Serial Port Timing............................................................55
SPI Serial Port Operation...........................................................56
Pin Descriptions......................................................................56
SPI Mode Operation...............................................................56
Communication Cycle—Instruction Plus Data..................56
Write .........................................................................................56
Read ..........................................................................................57
SPI Instruction Word (16 Bits)..................................................57
AD9522-4
SPI MSB/LSB First Transfers .....................................................57
EEPROM Operations .....................................................................60
Writing to the EEPROM ............................................................60
Reading from the EEPROM ......................................................60
Programming the EEPROM Buffer Segment..........................61
Register Section Definition Group.......................................61
IO_UPDATE (Operational Code 0x80) ..............................61
End-of-Data (Operational Code 0xFF) ...............................61
Pseudo-End-of-Data (Operational Code 0xFE).................61
Thermal Performance.....................................................................63
Register Map ....................................................................................64
Register Map Descriptions.............................................................68
Applications Information...............................................................82
Frequency Planning Using the AD9522 ..................................82
Using the AD9522 Outputs for ADC Clock Applications.....82
LVDS Clock Distribution...........................................................82
CMOS Clock Distribution.........................................................83
Outline Dimensions........................................................................84
Ordering Guide ...........................................................................84
Rev. A | Page 3 of 84

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AD9522-4
REVISION HISTORY
3/15—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Table 1 and Table 2....................................................... 5
Change to Input Frequency Parameter, Table 3 ........................... 8
Changes to Table 4............................................................................ 8
Changes to SDIO, SDO (Outputs) Parameter, Test
Conditions/Comments Column, Table 13 .................................. 13
Changes to Table 17........................................................................ 15
Change to VCP Supply Parameter, Table 18 ............................... 16
Change to Junction Temperature Parameter, Table 19 .............. 17
Changes to Pin 4 Description Column, Table 21 and Pin 22
Description Column, Table 21...................................................... 18
Removed Figure 13; Renumbered Sequentially.......................... 21
Added Test Circuits Section .......................................................... 26
Moved Figure 33 and Figure 34 .................................................... 26
Changes to Figure 33 and Figure 34............................................. 26
Changes to Mode 0: Internal VCO and Clock Distribution
Section.............................................................................................. 29
Deleted Configuration and Register Settings Section ............... 29
Changes to Figure 36...................................................................... 30
Changes to Figure 37...................................................................... 32
Changes to Figure 38...................................................................... 34
Changes to Configuration of the PLL Section and Charge Pump
(CP) Section .................................................................................... 35
Changes to On-Chip VCO Section, Figure 40, and PLL
Reference Inputs Section ............................................................... 36
Added Figure 42 and Figure 43; Renumbered Sequentially ..... 36
Changes to Reference Switchover Section................................... 37
Changes to Prescaler Section, A and B Counters Section, R and
N Divider Delays, and Table 29 .................................................... 38
Changes to Current Source Digital Lock Detect (CSDLD)
Section.............................................................................................. 39
Data Sheet
Changes to External VCXO/VCO Clock Input (CLK/CLK)
Section and Holdover Section ...................................................... 40
Changes to Frequency Status Monitors Section and VCO
Calibration Section......................................................................... 42
Changes to Figure 49 Caption ...................................................... 43
Added Table 31; Renumbered Sequentially ................................ 44
Changes to Zero Delay Operation Section and Internal Zero
Delay Mode Section ....................................................................... 45
Changes to Clock Distribution Section....................................... 46
Changes to VCO Divider Section and Channel Frequency
Division (0, 1, 2, and 3) Section.................................................... 47
Added Channel Divider Maximum Frequency Section............ 47
Changes to Duty Cycle and Duty-Cycle Correction Section and
Table 37 ............................................................................................ 48
Changes to Synchronizing the Outputs—SYNC Function
Section.............................................................................................. 49
Changes to Power-On Reset Section, Hardware Reset via
the RESET Pin Section, and Soft Reset via the Serial Port Section 51
Changes to Pin Descriptions Section and SPI Mode Operation
Section.............................................................................................. 56
Changes to SPI Instruction Word (16 Bits) Section .................. 57
Changes to Figure 66, Figure 67 Caption, and Figure 68.......... 58
Changes to EEPROM Operation Section.................................... 60
Changes to Table 49 ....................................................................... 64
Changes to Table 50 and Table 51 ................................................ 68
Changes to Table 53 ....................................................................... 69
Changes to Table 55 ....................................................................... 77
Change to Table 58 ......................................................................... 81
Change to Frequency Planning Using the AD9522 Section..... 82
Updated Outline Dimensions....................................................... 84
10/08—Revision 0: Initial Version
Rev. A | Page 4 of 84