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July 2016
HI-8436
32-Channel Ground/Open or Supply/Open
Low Threshold Sensor with SPI Interface
GENERAL DESCRIPTION
The HI-8436 is a 32-channel discrete-to-digital sensor
fabricated with Silicon-on-Insulator (SOI) technology
designed to interface with a Serial Peripheral Interface
(SPI).
Four banks of 8 sense inputs can be programmed as either
GND/Open or Supply/Open sensors. Supply/Open
sensing is also referred to as 28V/Open sensing.
All sense inputs are internally lightning protected to
DO160G, Section 22, Cat AZ, BZ and ZZ without external
components.
The sensing circuit window comparator thresholds are set
by programming the center threshold and hysteresis
registers to values from 0.4V to 5.2V. The digital values of
the sensed inputs can be read either one bank at a time or
all 4 banks with one command.
Each bank of sensors have a VWETn pin available for
application of a voltage to supply pull up current to the
GND/Open sensor.
Interface to the digital subsystem is simple CMOS logic
inputs and outputs. The logic pins are compatible with 3.3V
logic allowing direct connection to a wide range of
microcontrollers or FPGAs.
APPLICATION
· Avionics Discrete to Digital Sensing
PIN CONFIGURATIONS
VWET0 - 1
SENSE_0 - 2
SENSE_1 - 3
SENSE_2 - 4
SENSE_3 - 5
SENSE_4 - 6
SENSE_5 - 7
SENSE_6 - 8
SENSE_7 - 9
SENSE_8-10
SENSE_9-11
HI-8436PQI
HI-8436PQT
HI-8436PQM
33 - SENSE_27
32 - VWET3
31 - SENSE_26
30 - SENSE_25
29 - SENSE_24
28 - SENSE_23
27 - SENSE_22
26 - SENSE_21
25 - SENSE_20
24 - SENSE_19
23 - SENSE_18
44 Pin Plastic Quad Flat Pack (PQFP)
10mm x 10mm
FEATURES
· Robust CMOS Silicon-on-Insulator (SOI) technology
· 32-channel Programmable Sense Operation,
GND/Open or Supply/Open, 4 X 8 Input Sensors
· Programmable HI/LO Threshold and Hysteresis in
0.1V steps, from 0.4V to 5.2V.
· Single Low Voltage Supply Operation for low
thresholds applications.
· Logic Operation from 3.0V to 3.6V
· 20 MHz Serial Peripheral Interface (SPI)
· Lightning Protected Sense Inputs
· Internal Self-Test
VWET0 - 1
SENSE_0 - 2
SENSE_1 - 3
SENSE_2 - 4
SENSE_3 - 5
SENSE_4 - 6
SENSE_5 - 7
SENSE_6 - 8
SENSE_7 - 9
SENSE_8 -10
SENSE_9 -11
HI-8436PCI
HI-8436PCT
HI-8436PCM
33 - SENSE_27
32 - VWET3
31 - SENSE_26
30 - SENSE_25
29 - SENSE_24
28 - SENSE_23
27 - SENSE_22
26 - SENSE_21
25 - SENSE_20
24 - SENSE_19
23 - SENSE_18
44 Pin Plastic QFN
7mm x 7mm
(DS8436 Rev. D)
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www.holtic.com
07/16

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HI-8436
BLOCK DIAGRAM
MRB
SI
SO
CSN
SCK
VLOGIC
SPI
VLOGIC VWET0-3
4
SO_31-0
TEST
12 DAC
VALUE/HYSTERESIS
PSEN_3-0
4
DAC
THRESHOLDS
PD PU
HI LO HI LO
VREF
SENSE_7-0
VWET0
50k
VLOGIC
PSEN_n
3.3k
23.8k
LIGHTNING
PROTECTION
200k
200k
29k
PSEN_n
PSEN_n
VLOGIC
TESTHI
VTHI/10
+
-
+
TESTLO
-
VTLO/10
32
SO_31-24
8
SO_23-16
8
SO_15-8 8
SO_7-0 8
SENSE_15-8
SENSE_23-16
SENSE_31-24
8
8
8
GND
Figure 2.
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HI-8436
PIN DESCRIPTIONS
PIN FUNCTION
DESCRIPTION
VLOGIC
Supply
3.3V Power Supply for both sensors and logic.
VWET<0-3>
Supply
Inputs to supply current to sense lines in GND/Open operation. Each of the
4 banks of 8 inputs has a VWETn pin. 50kΩ to GND.
SENSE<31:0>
Discrete Input
4 banks of 8 discrete inputs programmable through the SPI to be either
GND/Open or Supply/Open.
The type of input is programmed by bank, PSEN<3:0> bits. “0” makes the
bank GND/Open sensors, “1” makes the bank SUPPLY/Open sensors
The status of the inputs SENSE<31:0> are stored in SO<31:0>
See SPI section for programming and reading sensors.
GND
Supply
0V Ground for Sensor and Logic.
SCK
Digital Input SPI Clock.
nCS Digital Input SPI Chip Select, Active Low, internal 30kΩ pull-up.
SI Digital Input SPI serial data input, internal 30kΩ pull-down.
SO Digital Output SPI serial data output.
nMR
Digital Input
SPI COMMANDS
Master Reset, Active Low, internal 30kΩ pull-up.
Table 1.
OP Code
R/W
# Data
Bytes
DESCRIPTION
0x02
W
1 Write Control Register
0x04
W
1 Write Program Sense Banks Register, PSEN<3:0>, to program SENSE Inputs
0x3A W
2 Write GND/Open Threshold Center Value and Hysteresis
0x3C W
2 Write Supply/Open Threshold Center Value and Hysteresis
0x1E W
1 Write Test Mode Data Register
0x82
R
1 Read Control Register
0x84
R
1 Read Program Sense Banks Register, to read programmed bank type
0xBA
R
2 Read GND/Open Threshold Center Value and Hysteresis
0xBC
0x9E
R
R
2 Read Supply/Open Threshold Center Value and Hysteresis
1 Read Test Mode Data Register
0x90
R
1 Read Bank 0, SOUT Register, SO<7:0>, status of SENSE<7:0> Inputs
0x92
R
1 Read Bank 1, SOUT Register, SO<15:8>, status of SENSE<15:8> Inputs
0x94
0x96
0xF8
R
R
R
1 Read Bank 2, SOUT Register, SO<23:16>, status of SENSE<23:16> Inputs
1 Read Bank 3, SOUT Register, SO<31:24>, status of SENSE<31:24> Inputs
4 Read All Banks, SOUT Register, SO<31:0>, status of SENSE<31:0> Inputs
Table 2.
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HI-8436
SERIAL PERIPHERAL
INTERFACE (SPI)
SPI BASICS
The HI-8436 uses a SPI (Serial Peripheral Interface) for host
access to internal registers which program the chip and store
sensor status. Host serial communication is enabled through
the active low, Chip Select (nCS) pin, and is accessed via a
four-wire interface consisting of Serial Data Input (SI) from the
host, Serial Data Output (SO) to the host, the Serial Clock
(SCK) and the nCS. All read / write cycles are completely self-
timed.
The SPI protocol specifies master and slave operation; the
HI-8436 operates as a SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes”. Without
describing details of the SPI modes, the HI-8436 operates in
Mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). The
host SPI logic must be set for Mode 0 for proper
communications with the HI-8436.
As seen in Figure 3, SPI Mode 0 holds SCK in the low state
when idle. The SPI protocol transfers serial data in 8-bit bytes.
Once nCS is asserted, the rising edge of SCK shifts the input
data into the master and slave devices, starting with each byte's
most-significant bit. A rising edge on nCS completes the serial
transfer and re-initializes the HI-8436 SPI for the next transfer.
If nCS goes high before a full byte is clocked by SCK, the
incomplete byte clocked into the device SI pin is discarded.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex), per Figure 3 below.
However the HI-8436 operates half duplex, maintaining high
impedance on the SO output, except when actually transmitting
serial data. When the HI-8436 is sending data on SO during
read operations, activity on its SI input is ignored. The host
likewise ignores its SI input activity while transmitting to the HI-
8436.
HI-8436 SPI INSTRUCTIONS
The SPI Instructions used to read, write and configure the
HI-8436 consist of an opcode and data bytes. Each SPI
instruction begins with an 8-bit opcode with the format shown
below. The most significant bit (MSB) specifies whether the
instruction is a write, “0”, or a read, “1”, transfer.
When nCS goes low, the first 8 rising edges of the SCK shift the
op code into the decoder register, MSB first. The SPI can be
clocked up to 20 MHz.
XXXXXXX
MSB 7 6 5 4 3 2 1 0 LSB
Figure 4. SPI OPCODE FORMAT
For write instructions, the next 8 rising SCK edges shift a data
byte into the buffer register. The specific instruction register is
loaded on the 8th rising SCK edge. This sequence is repeated
until the required number of data bytes for the instruction are
written.
For read instructions, the most significant bit of the requested
data word appears at the SO pin at the next falling SCK edge
after the last op code bit is clocked into the decoder. As in write
instructions, the number of data bytes varies with the read
instruction. SO data changes on the falling SCK edges.
Figure 5 to Figure 7 show read and write timing for single-byte,
dual-byte and four byte register operations. The instruction op
code is immediately followed by data bytes comprising the 8-bit
data bytes read or written. For a register read or write, nCS is
negated after all data bytes are transferred.
Table 2 summarizes the HI-8436 SPI instruction set.
SCK (SPI Mode 0)
SI
SO High Z
nCS
MSB
MSB
LSB
LSB
High Z
FIGURE 3. Generalized Single-Byte Transfer Using SPI Protocol Mode 0
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HI-8436
Note: SPI Instruction op-codes not shown in Table 2 are
“reserved” and must not be used. Further, these op-codes will
not provide meaningful data in response to a read instruction.
Two instruction bytes cannot be “chained”; nCS must be
negated after each instruction, and then reasserted for the
following Read or Write instruction.
SCK
0 1234567 0 1234567
MSB
SI
High Z
SO
Op-Code Byte
LSB
MSB
nCS
Data Byte 0
LSB
High Z
FIGURE 5. Single-Byte Read From a Register
0 1234567 0 1234567 0 1234567
SCK
SPI Mode 0
MSB
SI
LSB MSB
LSB MSB
LSB
High Z
SO
Op-Code Byte
Data Byte 1
Data Byte 0
nCS
FIGURE 6. 2-Byte SPI Write Example
012345670123456701234567 01234567 01234567
SCK
SPI Mode 0
MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB
SI
High Z
SO
Op-Code Byte
Data Byte 3
Data Byte 2
Data Byte 1
Data Byte 0
nCS
FIGURE 7. 4-Byte SPI Read Example
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