The HI-8436 uses a SPI (Serial Peripheral Interface) for host
access to internal registers which program the chip and store
sensor status. Host serial communication is enabled through
the active low, Chip Select (nCS) pin, and is accessed via a
four-wire interface consisting of Serial Data Input (SI) from the
host, Serial Data Output (SO) to the host, the Serial Clock
(SCK) and the nCS. All read / write cycles are completely self-
The SPI protocol specifies master and slave operation; the
HI-8436 operates as a SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes”. Without
describing details of the SPI modes, the HI-8436 operates in
Mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). The
host SPI logic must be set for Mode 0 for proper
communications with the HI-8436.
As seen in Figure 3, SPI Mode 0 holds SCK in the low state
when idle. The SPI protocol transfers serial data in 8-bit bytes.
Once nCS is asserted, the rising edge of SCK shifts the input
data into the master and slave devices, starting with each byte's
most-significant bit. A rising edge on nCS completes the serial
transfer and re-initializes the HI-8436 SPI for the next transfer.
If nCS goes high before a full byte is clocked by SCK, the
incomplete byte clocked into the device SI pin is discarded.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex), per Figure 3 below.
However the HI-8436 operates half duplex, maintaining high
impedance on the SO output, except when actually transmitting
serial data. When the HI-8436 is sending data on SO during
read operations, activity on its SI input is ignored. The host
likewise ignores its SI input activity while transmitting to the HI-
HI-8436 SPI INSTRUCTIONS
The SPI Instructions used to read, write and configure the
HI-8436 consist of an opcode and data bytes. Each SPI
instruction begins with an 8-bit opcode with the format shown
below. The most significant bit (MSB) specifies whether the
instruction is a write, “0”, or a read, “1”, transfer.
When nCS goes low, the first 8 rising edges of the SCK shift the
op code into the decoder register, MSB first. The SPI can be
clocked up to 20 MHz.
MSB 7 6 5 4 3 2 1 0 LSB
Figure 4. SPI OPCODE FORMAT
For write instructions, the next 8 rising SCK edges shift a data
byte into the buffer register. The specific instruction register is
loaded on the 8th rising SCK edge. This sequence is repeated
until the required number of data bytes for the instruction are
For read instructions, the most significant bit of the requested
data word appears at the SO pin at the next falling SCK edge
after the last op code bit is clocked into the decoder. As in write
instructions, the number of data bytes varies with the read
instruction. SO data changes on the falling SCK edges.
Figure 5 to Figure 7 show read and write timing for single-byte,
dual-byte and four byte register operations. The instruction op
code is immediately followed by data bytes comprising the 8-bit
data bytes read or written. For a register read or write, nCS is
negated after all data bytes are transferred.
Table 2 summarizes the HI-8436 SPI instruction set.
SCK (SPI Mode 0)
SO High Z
FIGURE 3. Generalized Single-Byte Transfer Using SPI Protocol Mode 0
HOLT INTEGRATED CIRCUITS