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Data Sheet
Octal Ultrasound Analog Front End
AD9674
FEATURES
8 channels of LNA, VGA, AAF, ADC, and digital RF decimator
Low power: 150 mW per channel, TGC mode, 40 MSPS;
62.5 mW per channel, CW mode; <30 mW in power-down
Time gain compensation (TGC) channel input referred noise:
0.82 nV/√Hz, maximum gain
Flexible power-down modes
Fast recovery from low power standby mode: <2 μs
Low noise preamplifier (LNA)
Input referred noise voltage: 0.78 nV/√Hz, gain = 21.6 dB
Programmable gain: 15.6 dB/17.9 dB/21.6 dB
0.1 dB compression: 1.00 V p-p/
0.75 V p-p/0.45 V p-p
Flexible active input impedance matching
Variable gain amplifier (VGA)
Attenuator range: 45 dB, linear in dB gain control
Postamplifier gain (PGA): 21 dB/24 dB/27 dB/30 dB
Antialiasing filter (AAF)
Programmable second-order low-pass filter (LPF) from 8 MHz
to 18 MHz or 13.5 MHz to 30 MHz and high-pass filter (HPF)
Analog-to-digital converter (ADC)
Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS
Configurable serial low voltage differential signaling (LVDS)
Continuous wave (CW) Doppler mode harmonic rejection I/Q
demodulator
Individual programmable phase rotation
Dynamic range per channel: >160 dBFS/√Hz
Close in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS input
Radio frequency (RF) digital HPF and decimation by 2
10 mm × 10 mm, 144-ball CSP_BGA
APPLICATIONS
Medical imaging/ultrasound
Nondestructive Testing (NDT)
GENERAL DESCRIPTION
The AD9674 is designed for low cost, low power, small size, and
ease of use for medical ultrasound. It contains eight channels of a
VGA with an LNA, a CW harmonic rejection I/Q demodulator
with programmable phase rotation, an AAF, an ADC, a digital
HPF, and RF decimation by 2.
Each channel features a maximum gain of up to 52 dB, a fully
differential signal path, and an active input preamplifier termination.
The channel is optimized for high dynamic performance and
low power in applications where a small package size is critical.
The LNA has a single-ended to differential gain that is selectable
through the serial port interface (SPI). Assuming a 15 MHz noise
bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is
94 dB. In CW Doppler mode, each LNA output drives an I/Q
demodulator that has independently programmable phase
rotation with 16 phase settings.
Power-down of individual channels is supported to increase battery
life for portable applications. Standby mode allows quick power-up
for power cycling. In CW Doppler operation, the VGA, AAF, and
ADC are powered down. The ADC contains several features
designed to maximize flexibility and minimize system cost, such as
a programmable clock, data alignment, and programmable digital
test pattern generation. The digital test patterns include built in
fixed patterns, built in pseudorandom patterns, and custom
user defined test patterns entered via the SPI.
Rev. A
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Tel: 781.329.4700
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Technical Support
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Last Content Update: 11/01/2016
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Data Sheet
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Sheet
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• Low Cost, Octal Ultrasound Receiver with On-Chip RF
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AD9674
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
ADC Timing Diagram................................................................. 9
CW Doppler Timing Diagram ................................................... 9
Absolute Maximum Ratings.......................................................... 11
Thermal Impedance ................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 15
TGC Mode................................................................................... 15
CW Doppler Mode..................................................................... 19
Theory of Operation ...................................................................... 20
TGC Operation........................................................................... 20
REVISION HISTORY
1/16—Revision A: Initial Version
Data Sheet
Analog Test Signal Generation ................................................. 31
CW Doppler Operation............................................................. 32
Digital RF Decimator..................................................................... 33
Vector Profile .............................................................................. 33
RF Decimator.............................................................................. 34
Digital Test Waveforms.............................................................. 34
Digital block Power Saving scheme ......................................... 35
Serial Port Interface (SPI)................................................................ 36
Hardware Interface..................................................................... 36
Memory Map .................................................................................. 38
Reading the Memory Map Table.............................................. 38
Reserved Locations .................................................................... 38
Default Values ............................................................................. 38
Logic Levels................................................................................. 38
Recommended Start-Up Sequence .......................................... 38
Memory Map Register Descriptions........................................ 46
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
Rev. A | Page 2 of 47

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Data Sheet
AD9674
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 PDWN STBY
DVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
CWD I/Q
DEMODULATOR
VGA
AAF
14-BIT
ADC
FILTER/
DECIMATOR
DRVDD
SERIALIZER LVDS
CWQ+
CWQ–
CWI+
CWI–
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
8 CHANNELS
NCO
SERIAL
PORT
INTERFACE
AD9674
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
Rev. A | Page 3 of 47

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AD9674
Data Sheet
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C),
fIN = 5 MHz, local oscillator (LO) band mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = midhigh, programmable gain
amplifier (PGA) gain = 27 dB, analog gain control, VGAIN = (GAIN+) − (GAIN−) = 1.6 V, AAF LPF cutoff = fSAMPLE/3 in Mode I1/Mode II,1 AAF
LPF cutoff = fSAMPLE/4.5 in Mode III1/Mode IV,1 HPF cutoff = LPF cutoff/12.00, Mode I1 = fSAMPLE = 40 MSPS, Mode II1 = fSAMPLE = 65 MSPS,
Mode III1 = fSAMPLE = 80 MSPS, Mode IV1 = fSAMPLE = 125 MSPS, RF decimator bypassed, digital filter bypassed, and low power LVDS mode,
unless otherwise noted. All gain setting options are listed, which can be configured via SPI registers, and all power supply currents and power
dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV).1
Table 1.
Parameter2
Test Conditions/Comments
Min Typ
LNA CHARACTERISTICS
Gain
Single-ended input to differential output
15.6/17.9/21.6 3
Single-ended input to single-ended
output
9.6/11.9/15.63
0.1 dB Input Compression Point
LNA gain = 15.6 dB
1.00
LNA gain = 17.9 dB
0.75
LNA gain = 21.6 dB
0.45
1 dB Input Compression Point
LNA gain = 15.6 dB
1.20
LNA gain = 17.9 dB
0.90
LNA gain = 21.6 dB
0.60
Input Common Mode (LI-x, LG-x)
2.2
Output Common Mode (LO-x)
Switch off
High-Z
Switch on
1.5
Output Common Mode (LOSW-x)
Switch off
High-Z
Switch on
1.5
Input Resistance (LI-x)
Input Capacitance (LI-x)
RFB = 300 Ω
RFB = 1350 Ω
RFB = ∞ (unterminated)
50
200
6
20
Input Referred Noise Voltage
RS = 0 Ω
LNA gain = 15.6 dB
0.83
LNA gain = 17.9 dB
0.82
LNA gain = 21.6 dB
0.78
Input SNR
Noise bandwidth = 15 MHz,
LNA gain = 21.6 dB
94
Input Referred Noise Current
2.6
FULL CHANNEL (TGC) CHARACTERISTICS
AAF Low-Pass Cutoff
−3 dB, programmable, low band mode 8
−3 dB, programmable, high band mode 13.5
In Range AAF Bandwidth Tolerance
±10
Group Delay Variation
Input Referred Noise Voltage
f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V
LNA gain = 15.6 dB
±350
0.96
LNA gain = 17.9 dB
0.90
LNA gain = 21.6 dB
0.82
Noise Figure
Active Termination Matched
Unterminated
RS = 50 Ω
LNA gain = 15.6 dB, RFB = 150 Ω
LNA gain = 17.9 dB, RFB = 200 Ω
LNA gain = 21.6 dB, RFB = 300 Ω
LNA gain = 15.6 dB
5.6
4.8
3.8
3.2
LNA gain = 17.9 dB
2.9
LNA gain = 21.6 dB
2.6
Correlated Noise Ratio
No signal, correlated/uncorrelated
−30
Rev. A | Page 4 of 47
Max
18
30
Unit
dB
dB
V p-p
V p-p
V p-p
V p-p
V p-p
V p-p
V
Ω
V
Ω
V
kΩ
pF
nV/√Hz
nV/√Hz
nV/√Hz
dB
pA/√Hz
MHz
MHz
%
ps
nV/√Hz
nV/√Hz
nV/√Hz
dB
dB
dB
dB
dB
dB
dB