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Data Sheet
Octal Ultrasound AFE with JESD204B
AD9675
FEATURES
8 channels of LNA, VGA, AAF, ADC, and digital RF decimator
Low power
150 mW per channel, TGC mode, 40 MSPS
62.5 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP_BGA
TGC channel input referred noise: 0.82 nV/√Hz,
maximum gain
Flexible power-down modes
Fast recovery from low power standby mode: 2 μs
Low noise preamplifier (LNA)
Input referred noise: 0.78 nV/√Hz, gain = 21.6 dB
Programmable gain: 15.6 dB, 17.9 dB, or 21.6 dB
0.1 dB compression: 1000 mV p-p, 750 mV p-p, or 450 mV p-p
Flexible active input impedance matching
Variable gain amplifier (VGA)
Attenuator range: 45 dB, linear in dB gain control
Postamp gain (PGA): 21 dB, 24 dB, 27 dB, or 30 dB
Antialiasing filter (AAF)
Programmable second-order low-pass filter (LPF) from
8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass
filter (HPF)
Analog-to-digital converter (ADC)
SNR: 75 dB, 14 bits up to 125 MSPS
JESD204B Subclass 0 coded serial digital outputs
CW Doppler mode harmonic rejection I/Q demodulator
Individual programmable phase rotation
Dynamic range per channel: 160 dBFS/√Hz
Close-in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS input
RF digital decimation by 2 and high-pass filter
APPLICATIONS
Medical imaging/ultrasound
Nondestructive testing (NDT)
GENERAL DESCRIPTION
The AD9675 is designed for low cost, low power, small size, and
ease of use for medical ultrasound. It contains eight channels of
a variable gain amplifier (VGA) with a low noise preamplifier
(LNA), a continuous wave (CW) harmonic rejection I/Q
demodulator with programmable phase rotation, an antialiasing
filter (AAF), an analog-to-digital converter (ADC), and a digital
high-pass filter and RF decimation by 2 for data processing and
bandwidth reduction.
Each channel features a maximum gain of up to 52 dB, a fully
differential signal path, and an active input preamplifier termina-
tion. The channel is optimized for high dynamic performance
and low power in applications where a small package size is critical.
The LNA has a single-ended to differential gain that is selectable
through the serial port interface (SPI). Assuming a 15 MHz
noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA
input SNR is 94 dB. In CW Doppler mode, each LNA output
drives an I/Q demodulator that has independently
programmable phase rotation with 16 phase settings.
Power-down of individual channels is supported to increase
battery life for portable applications. Standby mode allows quick
power-up for power cycling. In CW Doppler operation, the
VGA, AAF, and ADC are powered down. The ADC contains
features to maximize flexibility and minimize system cost, such
as a programmable clock, data alignment, and programmable
digital test pattern generation. The digital test patterns include
built-in fixed patterns, built-in pseudorandom patterns, and
custom user-defined test patterns entered via the SPI.
Rev. A
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AD9675* Product Page Quick Links
Last Content Update: 11/01/2016
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Documentation
Data Sheet
• AD9675: Octal Ultrasound AFE With JESD204B Data
Sheet
Reference Materials
Press
• JESD204B FPGA Debug Software Accelerates High-speed
Design
• Low Cost, Octal Ultrasound Receiver with On-Chip RF
Decimator and JESD204B Serial Interface
• Xilinx and Analog Devices Achieve JEDEC JESD204B
Interoperability
Design Resources
• AD9675 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
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AD9675
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Revision History ............................................................................... 2 
Functional Block Diagram .............................................................. 3 
Specifications..................................................................................... 4 
AC Specifications.......................................................................... 4 
Digital Specifications ................................................................... 7 
Switching Specifications .............................................................. 9 
Absolute Maximum Ratings.......................................................... 12 
Thermal Impedance ................................................................... 12 
ESD Caution................................................................................ 12 
Pin Configuration and Function Descriptions........................... 13 
Typical Performance Characteristics ........................................... 16 
TGC Mode................................................................................... 16 
CW Doppler Mode..................................................................... 20 
Theory of Operation ...................................................................... 21 
TGC Operation........................................................................... 21 
REVISION HISTORY
1/16—Revision A: Initial Version
Data Sheet
Digital Outputs and Timing ..................................................... 29 
Analog Test Tone Generation ................................................... 38 
CW Doppler Operation............................................................. 39 
Digital RF Decimator..................................................................... 40 
Vector Profile .............................................................................. 40 
RF Decimator.............................................................................. 41 
Digital Test Waveforms.............................................................. 41 
Digital Block Power Saving Scheme ........................................ 42 
Serial Port Interface (SPI).............................................................. 43 
Hardware Interface..................................................................... 43 
Memory Map .................................................................................. 45 
Reading the Memory Map Table.............................................. 45 
Recommended Start-Up Sequence .......................................... 45 
Memory Map Register Table..................................................... 47 
Memory Map Register Descriptions........................................ 59 
Outline Dimensions ....................................................................... 60 
Ordering Guide .......................................................................... 60 
Rev. A | Page 2 of 60

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Data Sheet
AD9675
FUNCTIONAL BLOCK DIAGRAM
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
LO
GENERATION
AVDD1 AVDD2 PDWN STBY
DVDD
CWD I/Q
DEMODULATOR
VGA
AAF
14-BIT
ADC
RF DECIMATOR
DRVDD
AD9675
SERIALIZER
CML
8 CHANNELS
CWQ+
CWQ–
CWI+
CWI–
SERDOUT1+ TO SERDOUT4+
SERDOUT1– TO SERDOUT4–
SYSREF+
SYSREF–
SYNCINB+
SYNCINB–
REFERENCE
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
Figure 1.
Rev. A | Page 3 of 60

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AD9675
Data Sheet
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C),
fIN = 5 MHz, low bandwidth mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = mid-high, PGA gain = 27 dB, analog
gain control, VGAIN (V) = (GAIN+) − (GAIN) = 1.6 V, AAF LPF cutoff = fSAMPLE/3 (Mode I/Mode II) = fSAMPLE/4.5 (Mode III/Mode IV),
HPF cutoff = LPF cutoff/12.00, Mode I = fSAMPLE = 40 MSPS, Mode II = fSAMPLE = 65 MSPS, Mode III = fSAMPLE = 80 MSPS, Mode IV = 125 MSPS,
RF decimator bypassed (Mode I/Mode II), RF decimator enabled (Mode III/Mode IV), digital high-pass filter bypassed, JESD204B link
parameters: M = 8 and L = 2, unless otherwise noted. All gain setting options are listed, which can be configured via SPI registers, and all
power supply currents and power dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV).
Table 1.
Parameter1
LNA CHARACTERISTICS
Gain
0.1 dB Input Compression Point
1 dB Input Compression Point
Input Common Mode (LI-x, LG-x)
Output Common Mode (LO-x)
Output Common Mode (LOSW-x)
Input Resistance (LI-x)
Test Conditions/Comments
Single-ended input to differential output
Single-ended input to single-ended output
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
Switch off
Switch on
Switch off
Switch on
RFB = 300 Ω, LNA gain = 21.6 dB
RFB = 1350 Ω, LNA gain = 21.6 dB
Input Capacitance (LI-x)
Input Referred Noise Voltage
Input Signal-to-Noise Ratio
Input Noise Current
FULL CHANNEL CHARACTERISTICS
AAF Low-Pass Cutoff
In Range AAF Bandwidth
Tolerance
Group Delay Variation
Input Referred Noise Voltage
Noise Figure
Active Termination Matched
Unterminated
RS = 0 Ω
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
Noise bandwidth = 15 MHz
Time gain control (TGC)
−3 dB, programmable, low bandwidth mode
−3 dB, programmable, high bandwidth mode
f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
LNA gain = 15.6 dB, RFB = 150 Ω
LNA gain = 17.9 dB, RFB = 200 Ω
LNA gain = 21.6 dB, RFB = 300 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.6 dB, RFB = ∞
Rev. A | Page 4 of 60
Min
8
13.5
Typ Max
15.6/17.9/21.6
9.6/11.9/15.6
1000
750
450
1200
900
600
2.2
High-Z
1.5
High-Z
1.5
50
200
6
22
0.83
0.82
0.78
94
2.6
±10
±350
0.96
0.90
0.82
18
30
5.6
4.8
3.8
3.2
2.9
2.6
Unit
dB
dB
mV p-p
mV p-p
mV p-p
mV p-p
mV p-p
mV p-p
V
Ω
V
Ω
V
Ω
Ω
pF
nV/√Hz
nV/√Hz
nV/√Hz
dB
pA/√Hz
MHz
MHz
%
ps
nV/√Hz
nV/√Hz
nV/√Hz
dB
dB
dB
dB
dB
dB