AD9877.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 AD9877 데이타시트 다운로드

No Preview Available !

FEATURES
Low cost 3.3 V CMOS MxFE™ for
MCNS-DOCSIS-, DVB-, DAVIC-compliant
set-top box and cable modem applications
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+®)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
Selectable interpolation filter
Analog Tx output level adjust
12-bit, 33 MSPS direct IF ADC
Dual 8-bit, 16.5 MSPS sampling IQ ADCs
Two 12-bit Σ-Δ auxiliary DACs
Direct interface to AD8321/AD8325 or
AD8322/AD8327 PGA cable driver
APPLICATIONS
Cable modems
Set-top boxes
Wireless modems
GENERAL DESCRIPTION
The AD9877 is a single-supply set-top box and cable modem
mixed-signal front end. The device contains a transmit path
interpolation filter, complete quadrature digital upconverter,
and transmit DAC. The receive path contains a 12-bit ADC and
dual 8-bit ADCs. All internally required clocks and an output
system clock are generated by the phase-locked loop (PLL) from
a single crystal or clock input.
The transmit path interpolation filter provides upsampling
factors of 12× or 16× with an output signal bandwidth as high
as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of
frequency tuning resolution can be generated by the direct
digital synthesizer (DDS). The transmit DAC resolution is 12 bits
and can run at sampling rates as high as 232 MSPS. Analog
output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to
preserve SNR when reduced output levels are required.
Mixed-Signal Front End
Set-Top Box, Cable Modem
AD9877
FUNCTIONAL BLOCK DIAGRAM
Tx DATA
SPORT
PROFILE
RxIQ DATA
Tx
PLL
4
2
INTER-
POLATOR
FILTER
DDS
COS
12
SIN
CONTROL FUNCTIONS
8
Rx
8
DAC
12
Σ-Δ
12
Σ-Δ
ADC
ADC
3
Tx
CA
SDELTA0
SDELTA1
REFCLK
I IN
Q IN
RxIF DATA
AD9877
12
ADC
IF IN
Figure 1.
The 12-bit ADC has excellent undersampling performance,
allowing it to typically deliver better than 10 ENOBs with IF
inputs up to 70 MHz. The 12-bit IF ADC can sample at a rate
up to 33 MHz, allowing it to process wideband signal inputs.
Two programmable Σ-Δ DACs are available and can be used to
control external components, such as variable gain amplifiers
(VGAs) or voltage-controlled tuners.
The AD9877 integrates a CA port that enables a host processor
to control the AD8321/AD8325 or AD8322/AD8327
programmable gain amplifier (PGA) cable drivers via the
MxFE SPORT.
The AD9877 is available in a 100-lead MQFP package. It offers
enhanced receive path undersampling performance and lower
cost compared to the pin-compatible AD9873. The AD9877 is
specified over the extended industrial (−40°C to +85°C)
temperature range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

No Preview Available !

AD9877* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Documentation
Application Notes
• AN-237: Choosing DACs for Direct Digital Synthesis
Data Sheet
• AD9877: Mixed-Signal Front End Set-Top Box, Cable
Modem Data Sheet
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Technical Articles
• High Integration Simplifies Signal Processing For CCDs
• MS-2210: Designing Power Supplies for High Speed ADC
Design Resources
• AD9877 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9877 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

No Preview Available !

AD9877
TABLE OF CONTENTS
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels ........................................................... 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Transmit Section......................................................................... 13
Clock and Oscillator Circuitry ................................................. 14
Programmable Clock Output REFCLK................................... 15
Reset and Transmit Power-Down ............................................ 16
Σ-Δ Outputs ................................................................................ 17
Register Map and Bit Definitions ................................................. 18
Register 0x00—Initialization .................................................... 19
Register 0x01—Clock Configuration....................................... 19
Register 0x02—Power-Down.................................................... 19
Register 0x03–0x06—Σ-Δ Control Words.............................. 19
Register 0x08—ADC Clock Configuration ............................ 20
Register 0x0C—Die Revision.................................................... 20
Register 0x0D—Tx Frequency Tuning Words LSBs.............. 20
Register 0x0E—DAC Gain Control ......................................... 20
Register 0x0F—Tx Path Configuration ................................... 20
Registers 0x10–0x1F—Burst Parameter .................................. 20
Serial Interface for Register Control ............................................ 22
General Operation of the Serial Interface ............................... 22
Instruction Byte .......................................................................... 22
Serial Interface Port Pin Description....................................... 22
MSB/LSB Transfers .................................................................... 22
Notes on Serial Port Operation ................................................ 23
Transmit Path (Tx) ......................................................................... 24
Transmit Timing......................................................................... 24
Data Assembler........................................................................... 24
Half-Band Filters (HBFs) .......................................................... 24
Cascaded Integrator-Comb (CIC) Filter................................. 24
Combined Filter Response........................................................ 25
Tx Signal Level Considerations ................................................ 27
Tx Throughput and Latency ..................................................... 27
Digital-to-Analog Converter .................................................... 27
Programming the AD8321/AD8325 or AD8322/AD8327 Cable
Driver Amplifier Gain Control..................................................... 29
Receive Path (Rx) ........................................................................... 30
ADC Theory of Operation........................................................ 30
Receive Timing ........................................................................... 30
Driving the Analog Inputs ........................................................ 30
Op Amp Selection Guide .......................................................... 31
ADC Differential Inputs............................................................ 31
ADC Voltage References ........................................................... 32
PCB Design Considerations.......................................................... 33
Component Placement .............................................................. 33
Power Planes and Decoupling .................................................. 33
Ground Planes ............................................................................ 33
Signal Routing............................................................................. 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
Rev. B | Page 2 of 36

No Preview Available !

REVISION HISTORY
5/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Changed OSCOUT to REFCLK....................................... Universal
Changed REF CLK to REFCLK........................................ Universal
Changes to Specifications.................................................................4
Changes to Figure 24 ......................................................................23
Updated Outline Dimensions........................................................35
Changes to Ordering Guide...........................................................35
AD9877
7/02—Rev. 0 to Rev. A
Edits to ORDERING GUIDE ..........................................................5
Edits to RESET AND TRANSMIT POWER-DOWN section..17
Revision 0: Initial Version
Rev. B | Page 3 of 36

No Preview Available !

AD9877
SPECIFICATIONS
VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8 and N = 4). ADC sample frequencies
derived from PLL (fMCLK), RSET = 4.02 kΩ, maximum fine gain, 75 Ω DAC load.
Table 1.
Parameter
SYSTEM CLOCK DAC SAMPLING, fSYSCLK
Frequency Range (N = 4)
Frequency Range (N = 3)
OSCIN and XTAL CHARACTERISTICS
Frequency Range
Duty Cycle
Input Impedance
MCLK JITTER
Cycle to Cycle (fMCLK derived from PLL)
Tx DAC CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error (using internal reference)
Offset Error
Reference Voltage (REFIO Level)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 42 MHz Carrier
Output Voltage Compliance Range
Wideband SFDR
5 MHz Analog Out, IOUT = 10 mA
65 MHz Analog Out, IOUT = 10 mA
Narrow-Band SFDR (±1 MHz Window)
65 MHz Analog Out, IOUT = 10 mA
Tx MODULATOR CHARACTERISTICS
I/Q Offset
Pass-Band Amplitude Ripple (f < fIQCLK/8)
Pass-Band Amplitude Ripple (f < fIQCLK/4)
Stop-Band Response (f > fIQCLK × 3/4)
Tx GAIN CONTROL
Gain Step Size
Gain Step Error
Settling Time, 1% (Full-Scale Step)
8-BIT ADC CHARACTERISTICS
Resolution
Conversion Rate
Pipeline Delay
Offset Matching Between I and Q ADCs
Gain Matching Between I and Q ADCs
Analog Input
Input Voltage Range
Differential Input Impedance
Full Power Bandwidth
Input Referred Noise
Test
Temp Level
Full II
Full II
Full II
25°C II
25°C III
25°C III
N/A N/A
Full II
Full I
25°C I
25°C I
25°C III
25°C III
25°C III
25°C III
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
25°C III
25°C III
25°C III
N/A N/A
Full II
N/A N/A
Min
3
35
4
−2.5
1.18
−0.5
48
48
53
50
Full II
25°C III
25°C III
25°C III
Typ Max
232
177
50
100||3
33
65
6
12
10
−1
±1.0
1.23
±2.5
±8
5
−110
20
+2.5
1.28
+1.5
55
51
69
55
±0.1
±0.5
−63
0.5
0.05
1.8
8
16.5
3.5
±8.0
±2.0
1
4||2
90
600
Unit
MHz
MHz
MHz
%
MΩ||pF
ps rms
Bits
mA
% FS
% FS
V
LSB
LSB
pF
dBc/Hz
V
dBc
dBc
dBc
dB
dB
dB
dB
dB
dB
μs
Bits
MHz
ADC cycles
LSBs
LSBs
Vppd
kΩ||pF
MHz
μV
Rev. B | Page 4 of 36