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Data Sheet
1.65 GHz Clock Fanout Buffer with
Output Dividers and Delay Adjust
AD9508
FEATURES
1.65 GHz differential clock inputs/outputs
10-bit programmable dividers, 1 to 1024, all integers
Up to 4 differential outputs or 8 CMOS outputs
Pin strapping capability for hardwired programming at
power-up
<115 fs rms broadband random jitter (see Figure 25)
Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz)
Excellent output-to-output isolation
Automatic synchronization of all outputs
Single 2.5 V/3.3 V power supply
Internal LDO (low drop-out) voltage regulator for enhanced
power supply immunity
Phase offset select for output-to-output coarse delay adjust
3 programmable output logic levels, LVDS, HSTL, and CMOS
Serial control port (SPI/I2C) or pin-programmable mode
Space-saving 24-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
GENERAL DESCRIPTION
The AD9508 provides clock fanout capability in a design that
emphasizes low jitter to maximize system performance. This
device benefits applications like clocking data converters with
demanding phase noise and low jitter requirements.
There are four independent differential clock outputs, each with
various types of logic levels available. Available logic types
include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS
(250 MHz). In 1.8 V CMOS output mode, the differential output
becomes two CMOS single-ended signals. The CMOS outputs
are 1.8 V logic levels, regardless of the operating supply voltage.
FUNCTIONAL BLOCK DIAGRAM
AD9508
CLK
CLK
SCLK/SCL/S0
SDIO/SDA/S1
SDO/S3
CS/S2
CONTROL
INTERFACE
SPI/I2C/PINS
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
PIN CONTROL RESET
Figure 1.
SYNC
Each output has a programmable divider that can be bypassed
or be set to divide by any integer up to 1024. In addition, the
AD9508 supports a coarse output phase adjustment between
the outputs.
The device can also be pin programmed for various fixed
configurations at power-up without the need for SPI or I2C
programming.
The AD9508 is available in a 24-lead LFCSP and operates from
a either a single 2.5 V or 3.3 V supply. The temperature range is
−40°C to +85°C.
Rev. F
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AD9508* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Evaluation Kits
• AD9508 Evaluation Board
Documentation
Data Sheet
• AD9508-DSCC: Military Data Sheet
• AD9508-EP: Enhanced Product Data Sheet
• AD9508: 1.65 GHz Clock Fanout Buffer with Output
Dividers and Delay Adjust Data Sheet
Reference Materials
Press
• Multi-output, 1.65-GHz Clock Buffer and Divider Delivers
Low Jitter to Optimize Noise Performance in Ultra-high-
speed Data Converters
Design Resources
• AD9508 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
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AD9508
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Electrical Characteristics............................................................. 4
Power Supply Current and Temperature Conditions .............. 4
Clock Inputs and Output DC Specifications ............................ 5
Output Driver Timing Characteristics ...................................... 6
Logic Inputs................................................................................... 7
Serial Port Specifications—SPI Mode........................................ 7
Serial Port Specifications—I2C Mode ........................................ 8
External Resistor Values For Pin Strapping Mode................... 9
Clock Output Additive Phase Noise .......................................... 9
Clock Output Additive Time Jitter........................................... 10
Absolute Maximum Ratings.......................................................... 11
Thermal Characteristics ............................................................ 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
Test Circuits..................................................................................... 20
Input/Output Termination Recommendations...................... 20
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 22
Detailed Block Diagram ............................................................ 22
Programming Mode Selection.................................................. 22
Data Sheet
Clock Input.................................................................................. 23
Clock Outputs............................................................................. 24
Clock Dividers ............................................................................ 24
Phase Delay Control .................................................................. 24
Reset Modes ................................................................................ 25
Power-Down Mode.................................................................... 25
Output Clock Synchronization................................................. 25
Power Supply............................................................................... 25
Thermally Enhanced Package Mounting Guidelines............ 25
Pin Strapping to Program on Power-Up ..................................... 26
Serial Control Port ......................................................................... 27
SPI/I2C Port Selection................................................................ 27
SPI Serial Port Operation.......................................................... 27
I2C Serial Port Operation .......................................................... 30
Register Map ................................................................................... 33
Register Map Bit Descriptions ...................................................... 34
Serial Port Configuration (Register 0x00) .............................. 34
Silicon Revision (Register 0x0A to Register 0x0D) ............... 34
Chip Level Functions (Register 0x12 to Register 0x14) ........ 34
OUT0 Functions (Register 0x15 to Register 0x1A)............... 35
OUT1 Functions (Register 0x1B to Register 0x20) ............... 36
OUT2 Functions (Register 0x21 to Register 0x26)................ 37
OUT3 Functions (Register 0x27 to Register 0x2C)............... 38
Packaging and Ordering Information ......................................... 40
Outline Dimensions................................................................... 40
Ordering Guide .......................................................................... 40
Rev. F | Page 2 of 40

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Data Sheet
REVISION HISTORY
4/15—Rev. E to Rev. F
Changes to Clock Outputs Section ...............................................24
Changes to Table 28 ........................................................................35
Changes to Table 30 ........................................................................36
Changes to Table 32 ........................................................................38
Changes to Table 34 ........................................................................39
11/14—Rev. D to Rev. E
Changes to Figure 1 ..........................................................................1
Moved Revision History Section.....................................................3
Changes to Table 12 ........................................................................12
Changes to Clock Outputs Section, Clock Dividers Section, and
Phase Delay Control Section .........................................................24
Changed Individual Clock Channel Power-Down Section to
Individual Clock Divider Power-Down Section .........................25
Changes to Individual Clock Divider Power-Down Section and
Output Clock Synchronization Section........................................25
Changes to Pin Strapping to Program on Power-up Section and
Table 15.............................................................................................26
Changes to Table 27 and Table 28 .................................................35
Changes to Table 29 and Table 30 .................................................36
Changes to Table 31 and Table 32 .................................................37
Changes to Table 33 ........................................................................38
Changes to Table 34 ........................................................................39
9/14—Rev. C to Rev. D
Changes to Table 1 ............................................................................3
Changes to Table 2 ............................................................................4
Changes to Figure 37 Caption; Added Figure 38; Renumbered
Sequentially ......................................................................................19
Changes to Clock Input Section and Table 14.............................23
AD9508
2/14—Rev. B to Rev. C
Changes to Table 14 ........................................................................22
10/13—Rev. A to Rev. B
Change to Figure 5 Caption...........................................................13
Change to Figure 13 Caption.........................................................14
Change to Figure 19 Caption.........................................................15
Change to Individual Clock Channel Power-Down Section ....23
Change to Write Section ................................................................27
Changes to Table 27 ........................................................................34
Changes to Table 29 ........................................................................35
Changes to Table 31 ........................................................................36
Changes to Table 33 ........................................................................37
4/13—Rev. 0 to Rev. A
Changes to Table 9 ............................................................................9
Changes to Figure 10 ......................................................................14
Changes to Figure 15 ......................................................................15
Changes to Figure 24 and Figure 26 .............................................16
Changes to Figure 27, Figure 29 to Figure 32..............................17
Changes to Figure 33 ......................................................................18
1/13—Revision 0: Initial Version
Rev. F | Page 3 of 40

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AD9508
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical values are given for VS = 3.3 V and 2.5 V and TA = 25°C; minimum and maximum values are given over the full VDD = 3.3 V + 5% down
to 2.5 V − 5% and TA = −40°C to +85°C variation; and input slew rate > 1 V/ns, unless otherwise noted.
POWER SUPPLY CURRENT AND TEMPERATURE CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
CURRENT CONSUMPTION
LVDS Configuration
HSTL Configuration
CMOS Configuration
Full Power-Down
TEMPERATURE
Ambient Temperature Range, TA
Junction Temperature, TJ
Min Typ
2.375 2.5
Max
3.465
165
122
194
131
92
141
122
85
6
−40 +25
182
134
213
144
101
185
134
94
10
+85
115
Unit Test Conditions/Comments
V Use supply voltage setting (2.5 V or 3.3 V) and
appropriate current consumption configuration
(see Current Consumption parameters in Table 1)
to calculate total power dissipation
mA Input clock: 1500 MHz in differential mode, all
LVDS output drivers at 1500 MHz
mA Input clock: 800 MHz in differential mode, all
LVDS output drivers at 200 MHz
mA Input clock: 1500 MHz in differential mode, all
HSTL output drivers at 1500 MHz
mA Input clock: 491.52 MHz in differential mode, all
output drivers at 491.52 MHz
mA Input clock: 122.88 MHz in differential mode, all
output drivers at 122.88 MHz
mA Input clock: 1500 MHz in differential mode, all
CMOS output drivers at 250 MHz, 10 pF load
mA Input clock: 800 MHz in differential mode, all
CMOS outputs drivers at 200 MHz, 10 pF load
mA Input clock: 100 MHz in differential mode, all
CMOS outputs drivers at 100 MHz, 10 pF load
mA
°C
°C Junction temperatures above 115°C can
degrade performance but no damage should
occur, unless the absolute temperature is
exceeded
Rev. F | Page 4 of 40