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Data Sheet
Dual PLL, Quad Input, Multiservice
Line Card Adaptive Clock Translator
AD9559
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually
no disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, G.824, G.825, and G.8261
Auto/manual holdover and reference switchover
Adaptive clocking allows dynamic adjustment of feedback
dividers for use in OTN mapping/demapping applications
Dual digital PLL architecture with four reference inputs
(single-ended or differential)
4x2 crosspoint allows any reference input to drive either PLL
Input reference frequencies from 2 kHz to 1250 MHz
Reference validation and frequency monitoring (2 ppm)
Programmable input reference switchover priority
20-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a
single differential LVDS/HSTL output or as 2 single-ended
CMOS outputs
Output frequencies: 262 kHz to 1250 MHz
Programmable 17-bit integer and 23-bit fractional
feedback divider in digital PLL
Programmable digital loop filter covering loop bandwidths
from 0.1 Hz to 2 kHz
Low noise system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Pin program function for easy frequency translation
configuration
Software controlled power-down
72-lead (10 mm × 10 mm) LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and SDH to OTN mapping/demapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient
control
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9559 is a low loop bandwidth clock multiplier that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9559 generates an output clock synchronized to up to four
external input references. The digital PLL allows for reduction
of input time jitter or phase noise associated with the external
references. The digitally controlled loop and holdover circuitry
of the AD9559 continuously generates a low jitter output clock
even when all reference inputs have failed.
The AD9559 operates over an industrial temperature range of
−40°C to +85°C. If a single DPLL version of this part is needed,
refer to the AD9557.
FUNCTIONAL BLOCK DIAGRAM
AD9559
CHANNEL 0A
DIVIDER
REFERENCE
INPUT
MONITOR
AND MUX
DIGITAL
PLL 0
ANALOG
PLL 0
DIGITAL
PLL 1
ANALOG
PLL 1
CLOCK
MULTIPLIER
EEPROM
SERIAL INTERFACE
(SPI OR I2C)
÷3 TO ÷11
HF DIVIDER 0
÷3 TO ÷11
HF DIVIDER 1
STATUS AND
CONTROL PINS
CHANNEL 0B
DIVIDER
CHANNEL 1A
DIVIDER
CHANNEL 1B
DIVIDER
STABLE
SOURCE
Figure 1.
Rev. C
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Technical Support
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AD9559* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Evaluation Kits
• AD9559 Evaluation Board
Documentation
Data Sheet
• AD9559: Dual PLL, Quad Input, Multiservice Line Card
Adaptive Clock Translator Data Sheet
Tools and Simulations
• AD9559 IBIS Model
Reference Materials
Press
• Dual Adaptive Clock Translator Supports Wide Range of
Wired Network Applications including OTN De-mapping
and High-density Line Cards
Product Selection Guide
• RF Source Booklet
Design Resources
• AD9559 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
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AD9559
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital PLL (DPLL) Core .......................................................... 34
Applications....................................................................................... 1
Loop Control State Machine..................................................... 36
General Description ......................................................................... 1
System Clock (SYSCLK)................................................................ 37
Functional Block Diagram .............................................................. 1
SYSCLK Inputs ........................................................................... 37
Revision History ............................................................................... 3
SYSCLK Multiplier..................................................................... 37
Specifications..................................................................................... 4
Output PLL (APLL) ....................................................................... 39
Supply Voltage............................................................................... 4
APLL Configuration .................................................................. 39
Supply Current.............................................................................. 4
APLL Calibration ....................................................................... 39
Power Dissipation......................................................................... 5
Clock Distribution.......................................................................... 40
System Clock Inputs (XOA, XOB) ............................................. 5
Clock Dividers ............................................................................ 40
Reference Inputs ........................................................................... 6
Output Enable............................................................................. 40
Reference Monitors ...................................................................... 7
Output Mode and Power-Down .............................................. 40
Reference Switchover Specifications.......................................... 7
Distribution Clock Outputs ........................................................ 8
Clock Distribution Synchronization........................................ 41
Status and Control.......................................................................... 42
Time Duration of Digital Functions ........................................ 10
Digital PLL (DPLL_0 and DPLL_1) ........................................ 10
Multifunction Pins (M0 to M5) ............................................... 42
IRQ Function .............................................................................. 42
Analog PLL (APLL_0 and APLL_1) ........................................ 10
Watchdog Timer......................................................................... 43
Digital PLL Lock Detection ...................................................... 10
EEPROM ..................................................................................... 43
Holdover Specifications............................................................. 10
Serial Control Port ......................................................................... 49
Serial Port Specifications—SPI Mode...................................... 11
Serial Port Specifications—I2C Mode ...................................... 12
SPI/I²C Port Selection................................................................ 49
SPI Serial Port Operation .......................................................... 49
Logic Inputs (RESET, M5 to M0)............................................. 12
Logic Outputs (M5 to M0)........................................................ 12
Jitter Generation ......................................................................... 13
Absolute Maximum Ratings.......................................................... 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 20
Input/Output Termination Recommendations .......................... 26
Getting Started ................................................................................ 27
Chip Power Monitor and Startup............................................. 27
Multifunction Pins at Reset/Power-Up ................................... 27
Device Register Programming Using a Register Setup File.. 27
Register Programming Overview............................................. 28
Theory of Operation ...................................................................... 31
Overview...................................................................................... 31
Reference Input Physical Connections.................................... 32
Reference Monitors .................................................................... 32
Reference Input Block................................................................ 32
Reference Switchover ................................................................. 33
I²C Serial Port Operation .......................................................... 53
Programming the I/O Registers ................................................... 56
Buffered/Active Registers.......................................................... 56
Write Detect Registers ............................................................... 56
Autoclear Registers..................................................................... 56
Register Access Restrictions...................................................... 56
Thermal Performance.................................................................... 57
Power Supply Partitions................................................................. 58
3.3 V Supplies.............................................................................. 58
1.8 V Supplies.............................................................................. 58
Bypass Capacitors for Pin 21 and Pin 33................................. 58
Register Map ................................................................................... 59
Register Map Bit Descriptions ...................................................... 72
Serial Control Port Configuration (Register 0x0000 to
Register 0x0005) ......................................................................... 72
Clock Part Family ID (Register 0x000C and Register 0x000D) 72
User Scratchpad (Register 0x000E and Register 0x000F)..... 73
General Configuration (Register 0x0100 to Register 0x0109) .. 73
IRQ Mask (Register 0x010A to Register 0x112) .................... 74
Rev. C | Page 2 of 120

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Data Sheet
System Clock (Register 0x0200 to Register 0x0207) ..............76
Reference Input A (Register 0x0300 to Register 0x031A) .....77
Reference Input B (Register 0x0320 to Register 0x033A)......78
Reference Input C (Register 0x0340 to Register 0x035A) .....79
Reference Input D (Register 0x0360 to Register 0x037A).....81
DPLL_0 Controls (Register 0x0400 to Register 0x0415).......82
APLL_0 Configuration (Register 0x0420 to Register 0x0423) .. 84
PLL_0 Output Sync and Clock Distribution (Register 0x0424
to Register 0x042E) .....................................................................85
DPLL_0 Settings for Reference Input A (REFA) (Register
0x0440 to Register 0x044C).......................................................87
DPLL_0 Settings for Reference Input B (REFB) (Register
0x044D to Register 0x0459).......................................................88
DPLL_0 Settings for Reference Input C (REFC) (Register
0x045A to Register 0x0466).......................................................89
DPLL_0 Settings for Reference Input D (REFD) (Register
0x0467 to Register 0x0473)........................................................90
DPLL_1 Controls (Register 0x0500 to Register 0x0515).......91
APLL_1 Configuration (Register 0x0520 to Register 0x0523)...93
PLL_1 Output Sync and Clock Distribution (Register 0x0524
to Register 0x052E) .....................................................................94
DPLL_1 Settings for Reference Input C (REFC) (Register
0x0540 to Register 0x054C).......................................................96
DPLL_1 Settings for Reference Input D (REFD) (Register
0x054D to Register 0x0559).......................................................97
REVISION HISTORY
5/13—Rev. B to Rev. C
Changes to Table 25 ........................................................................49
3/13—Rev. A to Rev. B
Changes to Device Register Programming Using a Register
Setup File Section ............................................................................27
Changed 101100 to 1101100, Table 25 .........................................49
12/12—Rev. 0 to Rev. A
Change to Features Section..............................................................1
Changes to DPLL Overview Section, Figure 35, and
Figure 36 ...........................................................................................34
Changes to EEPROM Upload Section and Manual EEPROM
Download Section ...........................................................................45
Changes to Table 25 ........................................................................49
AD9559
DPLL_1 Settings for Reference Input A (REFA) (Register
0x055A to Register 0x0566).......................................................98
DPLL_1 Settings for Reference Input B (REFB) (Register
0x0567 to Register 0x0573)........................................................99
Digital Loop Filter Coefficients (Register 0x0800 to Register
0x0817) .......................................................................................100
Common Operational Controls (Register 0x0A00 to Register
0x0A0E)......................................................................................101
PLL_0 Operational Controls (Register 0x0A20 to Register
0x0A24) ......................................................................................104
PLL_1 Operational Controls (Register 0x0A40 to Register
0x0A44) ......................................................................................106
Status ReadBack (Register 0x0D00 to Register 0x0D05).....107
IRQ Monitor (Register 0x0D08 to Register 0x0D10) ..........108
PLL_0 Read-Only Status (Register 0x0D20 to Register
0x0D2A) .....................................................................................110
PLL_1 Read-Only Status (Register 0x0D40 to Register
0x0D4A) .....................................................................................112
EEPROM Control (Register 0x0E00 to Register 0x0E03) ...113
EEPROM Storage Sequence (Register 0x0E10 to Register
0x0E3C) ......................................................................................113
Outline Dimensions......................................................................120
Ordering Guide .........................................................................120
Changes to Table 34 ........................................................................63
Changes to Table 91 ........................................................................87
Changes to Table 92, Table 96, and Table 97 ...............................88
Changes to Table 101 and Table 102.............................................89
Changes to Table 106 and Table 107.............................................90
Changes to Table 126 ......................................................................97
Changes to Table 127, Table 131, and Table 132 .........................97
Changes to Table 136 and Table 137.............................................98
Changes to Table 141 and Table 142.............................................99
Changes to Table 179 ....................................................................113
Updated Outline Dimensions......................................................120
7/12—Revision 0: Initial Version
Rev. C | Page 3 of 120

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AD9559
Data Sheet
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD3 = 3.3 V; VDD = 1.8 V; TA= 25°C, unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
SUPPLY VOLTAGE
VDD3
VDD
Min Typ
3.135 3.30
1.71 1.80
Max Unit Test Conditions/Comments
3.465 V
1.89 V
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are at the maximum supply voltage found in Table 1.
The test conditions for the typical (typ) supply current are at the typical supply voltage found in Table 1.
The test conditions for the minimum (min) supply current are at the minimum supply voltage found in Table 1.
Table 2.
Parameter
SUPPLY CURRENT FOR TYPICAL CONFIGURATION
Min
IVDD3
IVDD
SUPPLY CURRENT FOR ALL BLOCKS RUNNING
CONFIGURATION
IVDD3
IVDD
34
253
75
256
Typ
42
316
94
320
Max Unit Test Conditions/Comments
Typical values are for the Typical Configuration
parameter listed in Table 3
50 mA
380 mA
Maximum values are for the All Blocks Running
parameter listed in Table 3
113 mA
384 mA
Rev. C | Page 4 of 120