AD9162.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 AD9162 데이타시트 다운로드

No Preview Available !

Data Sheet
11-Bit/16-Bit, 12 GSPS,
RF Digital-to-Analog Converters
AD9161/AD9162
FEATURES
DAC update rate up to 12 GSPS (minimum)
Direct RF synthesis at 6 GSPS (minimum)
DC to 2.5 GHz in baseband 1× bypass mode
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
1.5 GHz to 7.5 GHz in Mix-Mode
Bypassable interpolation (1× or bypass mode)
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
Excellent dynamic performance
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
Instrumentation, automatic test equipment (ATE)
Radars and jammers
GENERAL DESCRIPTION
In baseband mode, wide bandwidth capability combines with
high dynamic range to support DOCSIS 3.1 cable infrastructure
compliance from the minimum of two carriers to full maximum
spectrum of 1.794 GHz. A 2× interpolator filter (FIR85) enables
the AD9161/AD9162 to be configured for lower data rates and
converter clocking to reduce the overall system power and ease
the filtering requirements. In Mix-Mode™ operation, the AD9161/
AD9162 can reconstruct RF carriers in the second and third
Nyquist zones up to 7.5 GHz while still maintaining exceptional
dynamic range. The output current can be programmed from
8 mA to 38.76 mA. The AD9161/AD9162 data interface consists
of up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
A serial peripheral interface (SPI) can configure the AD9161/
AD9162 and monitor the status of all registers. The AD9161/
AD9162 are offered in an 165-ball, 8.0 mm × 8.0 mm, 0.5 mm
pitch, CSP_BGA package and in an 169-ball, 11 mm × 11 mm,
0.8 mm pitch, CSP_BGA package, including a leaded ball
option for the AD9162.
The AD9161/AD91621 are high performance, 11-bit/16-bit
PRODUCT HIGHLIGHTS
digital-to-analog converters (DACs) that supports data rates to
6 GSPS. The DAC core is based on a quad-switch architecture
coupled with a 2× interpolator filter that enables an effective
DAC update rate of up to 12 GSPS in some modes. The high
dynamic range and bandwidth makes these DACs ideally suited
for the most demanding high speed radio frequency (RF) DAC
applications.
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1
compliance with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
HB
AD9161/AD9162
HB
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
TX_ENABLE
Figure 1.
CLK±
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

No Preview Available !

AD9161/AD9162
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
DAC Input Clock Overclocking Specifications........................ 4
Power Supply DC Specifications ................................................ 4
Serial Port and CMOS Pin Specifications ................................. 7
JESD204B Serial Interface Speed Specifications ...................... 8
SYSREF± to DAC Clock Timing Specifications....................... 8
Digital Input Data Timing Specifications ................................. 9
JESD204B Interface Electrical Specifications ........................... 9
AC Specifications........................................................................ 10
Absolute Maximum Ratings.......................................................... 12
Reflow Profile.............................................................................. 12
Thermal Management ............................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 17
AD9161 ........................................................................................ 17
AD9162 ........................................................................................ 27
Terminology .................................................................................... 41
Theory of Operation ...................................................................... 42
Serial Port Operation ..................................................................... 43
Data Format ................................................................................ 43
Serial Port Pin Descriptions...................................................... 43
Serial Port Options ..................................................................... 43
JESD204B Serial Data Interface.................................................... 45
JESD204B Overview .................................................................. 45
Physical Layer ............................................................................. 46
Data Link Layer .......................................................................... 49
Transport Layer .......................................................................... 57
JESD204B Test Modes ............................................................... 59
JESD204B Error Monitoring..................................................... 61
Hardware Considerations ......................................................... 63
Main Digital Datapath ................................................................... 64
Data Format ................................................................................ 64
Interpolation Filters ................................................................... 64
Digital Modulation..................................................................... 67
Inverse Sinc ................................................................................. 69
Downstream Protection ............................................................ 70
Interrupt Request Operation ........................................................ 71
Interrupt Service Routine.......................................................... 71
Applications Information .............................................................. 72
Hardware Considerations ......................................................... 72
Analog Interface Considerations.................................................. 75
Analog Modes of Operation ..................................................... 75
Clock Input.................................................................................. 76
Shuffle Mode............................................................................... 77
DLL............................................................................................... 77
Voltage Reference ....................................................................... 77
Temperature Sensor ................................................................... 78
Analog Outputs .......................................................................... 78
Start-Up Sequence.......................................................................... 80
Register Summary .......................................................................... 82
Register Details ............................................................................... 88
Outline Dimensions ..................................................................... 138
Ordering Guide ........................................................................ 139
REVISION HISTORY
9/2016—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Change to AC Specifications Section........................................... 10
Added Reflow Profile Section, Thermal Management Section,
and Figure 3, Renumbered Sequentially...................................... 12
Changes to Figure 80...................................................................... 30
Changes to Link Delay Setup Example, With Known Delays
Section.............................................................................................. 54
Changes to Table 25 ....................................................................... 57
Moved Figure 188........................................................................... 77
Added Temperature Sensor Section............................................. 78
Changes to Table 46 ....................................................................... 87
Changes to Table 47 ....................................................................... 99
Changes to Ordering Guide ........................................................ 139
5/2016—Revision 0: Initial Version
Rev. A | Page 2 of 139

No Preview Available !

Data Sheet
AD9161/AD9162
SPECIFICATIONS
DC SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, DAC output full-scale current (IOUTFS) = 40 mA, and TA = −40°C to
+85°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
AD9161
DAC Update Rate
Minimum
Maximum
Maximum
Adjusted4
AD9162
DAC Update Rate
Minimum
Maximum
Maximum
Adjusted4
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK−)
Differential Input Power
Common-Mode Voltage
Input Impedance5
TEMPERATURE DRIFT
Gain
Reference Voltage
TEMPERATURE SENSOR
Accuracy
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
VDD25_DAC
VDD12A6
VDD12_CLK6
VNEG_N1P2
DIGITAL SUPPLY VOLTAGES
DVDD
IOVDD7
SERDES SUPPLY VOLTAGES
VDD_1P2
VTT_1P2
Test Conditions/Comments
Min
11
VDDx1 = 1.3 V ± 2%2
VDDx1 = 1.3 V ± 2%2, FIR853 2× interpolator enabled
VDDx1 = 1.3 V ± 2%2, minimum 2× interpolation
6
12
3
16
VDDx1 = 1.3 V ± 2%2
VDDx1 = 1.3 V ± 2%2, FIR853 2× interpolator enabled
VDDx1 = 1.3 V ± 2%2
6
12
6
RSET = 9.76 kΩ
RSET = 9.76 kΩ
RLOAD = 90 Ω differential on-chip
AC-coupled
3 GSPS input clock
7.37
35.8
−20
After one-point calibration (see the Temperature
Sensor section )
Includes VDD12_DCD/DLL
Can connect to VDD_1P2
2.375
1.14
1.14
−1.26
1.14
1.71
1.14
1.14
Typ
6.4
12.8
3.2
6.4
12.8
6.4
±2.7
±1.7
−1.7
8
38.76
0
0.6
90
105
75
±5
1.19
2.5
1.2
1.2
−1.2
1.2
2.5
1.2
1.2
Max Unit
Bit
1.5 GSPS
GSPS
GSPS
GSPS
Bit
1.5 GSPS
GSPS
GSPS
GSPS
LSB
LSB
%
8.57 mA
41.3 mA
+10 dBm
V
ppm/°C
ppm/°C
%
V
2.625
1.326
1.326
−1.14
V
V
V
V
1.326 V
3.465 V
1.326 V
1.326 V
Rev. A | Page 3 of 139

No Preview Available !

AD9161/AD9162
Data Sheet
Parameter
DVDD_1P2
PLL_LDO_VDD12
PLL_CLK_VDD12
SYNC_VDD_3P3
BIAS_VDD_1P2
Test Conditions/Comments
Can connect to PLL_LDO_VDD12
Can connect to VDD_1P2
Min
1.14
1.14
1.14
3.135
1.14
Typ
1.2
1.2
1.2
3.3
1.2
Max
1.326
1.326
1.326
3.465
1.326
Unit
V
V
V
V
V
1 VDDx is VDD12_CLK, DVDD, VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any clock speed over 5.1 GSPS requires a maximum junction temperature of 105°C to avoid
damage to the device. See Table 11 for details on maximum junction temperature permitted for certain clock speeds.
2 See Table 2 for the complete details on the guaranteed speed performance.
3 FIR85 is the finite impulse response filter with 85 dB digital attenuation that implements 2× NRZ mode.
4 The adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9162, the minimum interpolation factor is 1.
Therefore, with fDAC = 6 GSPS, fDAC adjusted = 6 GSPS. For the AD9161, the minimum interpolation is 2×. Therefore, with fDAC = 6 GSPS, fDAC adjusted = 3 GSPS. When
FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 × (DAC clock input frequency), and the minimum interpolation increases to 2× (interpolation
value). Thus, for the AD9162, with FIR85 enabled and DAC clock = 6 GSPS, fDAC = 12 GSPS, minimum interpolation = 2×, and the adjusted DAC update rate = 6 GSPS.
5 See the Clock Input section for more details.
6 For the lowest noise performance, use a separate power supply filter network for the VDD12_CLK and the VDD12A pins.
7 IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.
DAC INPUT CLOCK OVERCLOCKING SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Maximum guaranteed speed using the temperatures and voltages conditions as shown in Table 2, where VDDx is VDD12_CLK, DVDD,
VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any DAC clock speed over 5.1 GSPS requires a maximum junction temperature of
105°C to avoid damage to the device. See Table 11 for details on maximum junction temperature permitted for certain clock speeds.
Table 2.
Parameter1
MAXIMUM DAC UPDATE RATE
VDDx = 1.2 V ± 5%
VDDx = 1.2 V ± 2%
VDDx = 1.3 V ± 2%
Test Conditions/Comments
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
Min Typ Max Unit
6.0 GSPS
5.6 GSPS
5.4 GSPS
6.1 GSPS
5.8 GSPS
5.6 GSPS
6.4 GSPS
6.2 GSPS
6.0 GSPS
1 TJMAX is the maximum junction temperature.
POWER SUPPLY DC SPECIFICATIONS
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.
Table 3.
Parameter
8 LANES, 2× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
Test Conditions/Comments
Numerically controlled oscillator (NCO) on,
FIR85 on
Includes VDD12_DCD/DLL
Min Typ Max
−119
93.8
3.7
229
−112
621.3
2.5
100
150
279
971
2.7
Unit
mA
µA
mA
mA
mA
mA
Rev. A | Page 4 of 139

No Preview Available !

Data Sheet
Parameter
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
8 LANES, 6× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
NCO ONLY MODE, 5 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
8 LANES, 4× INTERPOLATION (80%), 5 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V (Includes VDD12_DCD/DLL)
DVDD = 1.2 V
IOVDD1 = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
Test Conditions/Comments
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
NCO on, FIR85 on
Includes VDD12_DCD/DLL
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
AD9161/AD9162
Min Typ Max Unit
425.5
62
84.4
9.3
550
86
106
11
mA
mA
mA
mA
93.8
3.7
228.7
−120.7
598.4
2.5
443.4
72.3
81.8
9.4
mA
µA
mA
mA
mA
mA
mA
mA
mA
mA
−119
93.7
10
340.6
−112
100
150
432
mA
µA
mA
mA
Includes VDD12_DCD/DLL
425.5
2.5
753
2.7
mA
mA
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
NCO on, FIR85 off (unless otherwise noted)
1.4 34 mA
1.0 14.1 mA
0.13 1.5 mA
0.32 0.43 mA
At 6 GSPS
−127.4
102
80
340.5
408
−120.2
108
150
432.4
mA
µA
mA
mA
mA
NCO on, FIR85 off
NCO off, FIR85 on
NCO on, FIR85 on
NCO on, FIR85 on, at 6 GSPS
665.4
706.5
894.6
1090
2.5
1033
2.7
mA
mA
mA
mA
mA
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
411.2
52.1
85.8
9.3
550
73
105
11
mA
mA
mA
mA
Rev. A | Page 5 of 139