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Data Sheet
Quad PLL, Quad Input, Multiservice Line
Card Adaptive Clock Translator
AD9554-1
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually no
disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and
ITU-T G.8261
Auto/manual holdover and reference switchover
Adaptive clocking allows dynamic adjustment of feedback
dividers for use in OTN mapping/demapping applications
Quad digital phase-locked loop (DPLL) architecture with four
reference inputs (single-ended or differential)
4 × 4 crosspoint allows any reference input to drive any PLL
Input reference frequencies from 2 kHz to 1000 MHz
Reference validation and frequency monitoring: 2 ppm
Programmable input reference switchover priority
20-bit programmable input reference divider
4 differential clock outputs with each differential pair
configurable as HCSL, LVDS-compatible, or LVPECL-
compatible
Output frequency range: 430 kHz to 941 MHz
Programmable 18-bit integer and 24-bit fractional feedback
divider in digital PLL
Programmable loop bandwidths from 0.1 Hz to 4 kHz
56-lead (8 mm × 8 mm) LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and synchronous digital hierarchy (SDH) to optical
transport network (OTN) mapping/demapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient
control
Cable infrastructure
Data communications
Professional video
GENERAL DESCRIPTION
The AD9554-1 is a low loop bandwidth clock translator that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9554-1 generates an output clock synchronized to up to four
external input references. The digital PLLs (DPLLs) allow
reduction of input time jitter or phase noise associated with the
external references. The digitally controlled loop and holdover
circuitry of the AD9554-1 continuously generates a low jitter
output clock even when all reference inputs have failed.
The AD9554-1 operates over an industrial temperature range of
−40°C to +85°C. The AD9554 is a version of this device with
two outputs per PLL. If a single or dual DPLL version of this
device is needed, refer to the AD9557 or AD9559, respectively.
STABLE
SOURCE
FUNCTIONAL BLOCK DIAGRAM
STATUS AND
CONTROL PINS
REFERENCE
INPUT
MONITOR
AND MUX
CLOCK
MULTIPLIER
SERIAL INTERFACE
(SPI OR I2C)
DIGITAL
PLL0
DIGITAL
PLL1
DIGITAL
PLL2
DIGITAL
PLL3
ANALOG
PLL0
ANALOG
PLL1
ANALOG
PLL2
ANALOG
PLL3
÷3 TO ÷11
P0 DIVIDER
÷3 TO ÷11
P1 DIVIDER
÷3 TO ÷11
P2 DIVIDER
÷3 TO ÷11
P3 DIVIDER
AD9554-1
Figure 1.
Q0_B DIVIDER
Q1_B DIVIDER
Q2_B DIVIDER
Q3_B DIVIDER
Rev. B
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AD9554-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital PLL (DPLL) Core .......................................................... 33
Applications....................................................................................... 1
Loop Control State Machine..................................................... 36
General Description ......................................................................... 1
System Clock (SYSCLK)................................................................ 37
Functional Block Diagram .............................................................. 1
SYSCLK Inputs ........................................................................... 37
Revision History ............................................................................... 4
SYSCLK Multiplier..................................................................... 37
Specifications..................................................................................... 5
Output Analog PLL (APLL).......................................................... 39
Supply Voltage............................................................................... 5
APLL Configuration .................................................................. 39
Supply Current.............................................................................. 5
APLL Calibration ....................................................................... 39
Power Dissipation......................................................................... 6
Clock Distribution.......................................................................... 40
System Clock Inputs (XOA, XOB) ............................................. 6
Clock Dividers ............................................................................ 40
Reference Inputs ........................................................................... 7
Output Amplitude and Power-Down ...................................... 40
Reference Monitors ...................................................................... 8
Clock Distribution Synchronization........................................ 41
Reference Switchover Specifications.......................................... 8
Distribution Clock Outputs ........................................................ 9
Status and Control.......................................................................... 42
Multifunction Pins (M0 to M3 and M5 to M7) ......................... 42
Time Duration of Digital Functions ........................................ 11
Digital PLL (DPLL_0, DPLL_1, DPLL_2, and DPLL_3) ...... 11
IRQ Function .............................................................................. 42
Watchdog Timer......................................................................... 43
Analog PLL (APLL_0, APLL_1, APLL_2, and APLL_3)...... 11
Serial Control Port ......................................................................... 44
Digital PLL Lock Detection ...................................................... 12
SPI/I²C Port Selection................................................................ 44
Holdover Specifications............................................................. 12
SPI Serial Port Operation .......................................................... 44
Serial Port Specifications—Serial Port Interface (SPI) Mode .... 12
Serial Port Specifications—I2C Mode ...................................... 13
I²C Serial Port Operation .......................................................... 47
Programming the I/O Registers ................................................... 50
Logic Inputs (RESET, M0 to M3, M5 to M7) ......................... 14
Logic Outputs (M0 to M3 and M5 to M7).............................. 14
Jitter Generation ......................................................................... 14
Absolute Maximum Ratings.......................................................... 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 20
Input/Output Termination Recommendations .......................... 23
Getting Started ................................................................................ 24
Chip Power Monitor and Startup............................................. 24
Multifunction Pins at Reset/Power-Up ................................... 24
Device Register Programming Using a Register Setup File....... 24
Register Programming Overview............................................. 28
Theory of Operation ...................................................................... 31
Overview...................................................................................... 31
Reference Input Physical Connections.................................... 32
Reference Monitors .................................................................... 32
Reference Input Block................................................................ 32
Reference Switchover ................................................................. 33
Buffered/Active Registers.......................................................... 50
Write Detect Registers ............................................................... 50
Autoclear Registers..................................................................... 50
Register Access Restrictions...................................................... 50
Thermal Performance.................................................................... 51
Power Supply Partitions................................................................. 52
VDD Supplies ............................................................................. 52
VDD_SP Supply ......................................................................... 52
Register Map ................................................................................... 53
Register Map Bit Descriptions ...................................................... 63
Serial Control Port Configuration (Register 0x0000 to
Register 0x0001) ......................................................................... 63
Clock Part Family ID (Register 0x0003 to Register 0x0006)..... 63
SPI Version (Register 0x000B).................................................. 64
Vendor ID (Register 0x000C to Register 0x000D) ................ 64
IO_Update (Register 0x000F)................................................... 64
General Configuration (Register 0x0100 to Register 0x010E).. 64
IRQ Mask (Register 0x010F to Register 0x011F)................... 65
System Clock (Register 0x0200 to Register 0x0208) ............. 67
Rev. B | Page 2 of 99

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Data Sheet
Reference Input A (Register 0x0300 to Register 0x031E)......68
Reference Input B (Register 0x0320 to Register 0x033E) ......70
Reference Input C (Register 0x0340 to Register 0x035E)......70
Reference Input D (Register 0x0360 to Register 0x037E) .....70
DPLL_0 Controls (Register 0x0400 to Register 0x041E) ......70
APLL_0 Configuration (Register 0x0430 to Register 0x0434)...72
Output PLL_0 (APLL_0) Sync and Clock Distribution
(Register 0x0434 to Register 0x043E).......................................73
DPLL_0 Settings for Reference Input A (REFA)
(Register 0x0440 to Register 0x044C) ......................................74
DPLL_0 Settings for Reference Input B (REFB)
(Register 0x044D to Register 0x0459)......................................75
DPLL_0 Settings for Reference Input C (REFC)
(Register 0x045A to Register 0x0466) ......................................76
DPLL_0 Settings for Reference Input D (REFD)
(Register 0x0467 to Register 0x0473).......................................77
DPLL_1 Controls (Register 0x0500 to Register 0x051E) ......78
APLL_1 Configuration (Register 0x0530 to Register 0x0533)...78
PLL_1 Output Sync and Clock Distribution (Register 0x0534
to Register 0x053E) .....................................................................78
DPLL_1 Settings for Reference Input A (REFA)
(Register 0x0540 to Register 0x054C) ......................................78
DPLL_1 Settings for Reference Input B (REFB)
(Register 0x054D to Register 0x0559)......................................78
DPLL_1 Settings for Reference Input C (REFC)
(Register 0x055A to Register 0x0566) ......................................79
DPLL_1 Settings for Reference Input D (REFD)
(Register 0x0567 to Register 0x0573).......................................79
DPLL_2 Controls (Register 0x0600 to Register 0x061E) ......79
APLL_2 Configuration (Register 0x0630 to Register 0x0633)...79
PLL_2 Output Sync and Clock Distribution (Register 0x0634
to Register 0x063E) .....................................................................79
DPLL_2 Settings for Reference Input A (REFA)
(Register 0x0640 to Register 0x064C) ......................................79
DPLL_2 Settings for Reference Input B (REFB)
(Register 0x064D to Register 0x0659)......................................79
DPLL_2 Settings for Reference Input C (REFC)
(Register 0x065A to Register 0x0666) ......................................79
DPLL_2 Settings for Reference Input D (REFD)
(Register 0x0667 to Register 0x0673).......................................79
AD9554-1
DPLL_3 Controls (Register 0x0700 to Register 0x071E) ...........79
APLL_3 Configuration (Register 0x0730 to Register 0x0733) ..79
PLL_3 Output Sync and Clock Distribution (Register 0x0734
to Register 0x073E).....................................................................79
DPLL_3 Settings for Reference Input A (REFA)
(Register 0x0740 to Register 0x074C) ......................................79
DPLL_3 Settings for Reference Input B (REFB)
(Register 0x074D to Register 0x0759)......................................79
DPLL_3 Settings for Reference Input C (REFC)
(Register 0x075A to Register 0x0766)......................................80
DPLL_3 Settings for Reference Input D (REFD)
(Register 0x0767 to Register 0x0773).......................................80
Digital Loop Filter Coefficients (Register 0x0800 to
Register 0x0817)..........................................................................80
Common Operational Controls (Register 0x0A00 to
Register 0x0A0E) ........................................................................81
IRQ Clearing (Register 0x0A05 to Register 0x0A14) ............83
PLL_0 Operational Controls (Register 0x0A20 to
Register 0x0A24).........................................................................86
PLL_1 Operational Controls (Register 0x0A40 to
Register 0x0A44).........................................................................88
PLL_2 Operational Controls (Register 0x0A60 to
Register 0x0A64).........................................................................88
PLL_3 Operational Controls (Register 0x0A80 to
Register 0x0A84).........................................................................88
Voltage Regulator (Register 0x0B00 to Register 0x0B01)......88
Status Readback (Register 0x0D01 to Register 0x0D05) .......88
IRQ Monitor (Register 0x0D08 to Register 0x0D16) ............90
PLL_0 Read Only Status (Register 0x0D20 to
Register 0x0D2A)........................................................................93
PLL_1 Read Only Status (Register 0x0D40 to
Register 0x0D4A)........................................................................95
PLL_2 Read Only Status (Register 0x0D60 to
Register 0x0D6A)........................................................................95
PLL_3 Read Only Status (Register 0x0D80 to
Register 0x0D8A)........................................................................95
Outline Dimensions........................................................................99
Ordering Guide ...........................................................................99
Rev. B | Page 3 of 99

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AD9554-1
REVISION HISTORY
10/2016—Rev. A to Rev. B
Changes to Figure 2........................................................................ 17
Deleted Figure 3; Renumbered Sequentially............................... 20
Changes to Device Register Programming Using a Register
Setup File Section ........................................................................... 24
Added Figure 26; Renumbered Sequentially .............................. 25
Added Figure 27.............................................................................. 26
Added Figure 28.............................................................................. 27
Added Figure 29.............................................................................. 28
Changes to Register Programming Overview Section .............. 28
Changes to DPLL Feedback Dividers Section ............................ 30
Changes to DPLL Phase Lock Detector Section......................... 35
Change to APLL Calibration Section........................................... 39
Changes to Table 62........................................................................ 73
Added Endnote 1, Table 67 ........................................................... 75
Changes to Table 73, Table 75, and Table 76............................... 77
Changes to Table 77, Table 78, Table 79, and Table 80 .............. 78
Changes to Table 82, Table 83, Table 84, Table 85,
and Table 86..................................................................................... 79
Changes to Table 87, Table 88, Table 89, and Table 90 .............. 80
Changes to Table 91 and Table 92 ................................................ 82
Changes to Table 94........................................................................ 83
Changes to Table 122...................................................................... 96
Data Sheet
8/2014—Rev. 0 to Rev. A
Added Bandwidth (fREF = 19.44 MHz; fOUT = 156.25 MHz;
fLOOP = 50 Hz) Parameters; Table 18 ............................................. 15
Changes to Figure 3........................................................................ 20
Changes to Figure 27...................................................................... 31
Changes to APLL Calibration Section......................................... 36
Changes to Output Amplitude and Power-Down Section........ 37
Changes to Table 69 ....................................................................... 71
4/2014—Revision 0: Initial Version
Rev. B | Page 4 of 99

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Data Sheet
AD9554-1
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD = 1.8 V, TA = 25°C, unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
SUPPLY VOLTAGE FOR 1.8 V OPERATION
VDD_SP
VDD
SUPPLY VOLTAGE FOR 1.5 V OPERATION
VDD_SP
VDD
Min Typ Max
1.47 1.8
1.71 1.8
2.625
1.89
1.47 1.5
1.47 1.5
2.625
1.53
Unit
V
V
V
V
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are at the maximum supply voltage found in Table 1. The test conditions for
the typical (typ) supply current are at the typical supply voltage found in Table 1. The test conditions for the minimum (min) supply
current are at the minimum supply voltage found in Table 1.
Table 2.
Parameter
SUPPLY CURRENT FOR TYPICAL CONFIGURATION
IVDD_SP
IVDD
SUPPLY CURRENT FOR ALL BLOCKS RUNNING CONFIGURATION
IVDD_SP
IVDD
Min Typ Max Unit Test Conditions/Comments
Typical values are for the Typical
Configuration parameter
listed in Table 3; valid for both 1.5 V and 1.8 V
operation
0.01 0.04 0.1 mA
450 513 560 mA
Maximum values are for the All Blocks
Running parameter
listed in Table 3; valid for both 1.5 V and 1.8 V
operation
0.01 0.04 0.1 mA
450 566 650 mA
Rev. B | Page 5 of 99