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16-Bit, 10 MHz Bandwidth, 30 MSPS to
160 MSPS Continuous Time Sigma-Delta ADC
AD9261
FEATURES
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: 87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 340 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
2.5 MHz/5 MHz/10 MHz
Output data rate: 30 MSPS to 160 MSPS
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
APPLICATIONS
Data acquisition
Automated test equipment
Instrumentation
Medical imaging
GENERAL DESCRIPTION
The AD9261 is a single 16-bit analog-to-digital converter
(ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves 87 dBc of dynamic range over a 10 MHz
input bandwidth. The integrated features and characteristics
unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
The AD9261 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversam-
pled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate from 30 MSPS to 160 MSPS,
enabling a more efficient and direct interface.
VIN+
VIN–
VREF
CFILT
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
Σ -Δ
MODULATOR
LOW-PASS
DECIMATION
FILTER
SAMPLE
RATE
CONVERTER
CMOS
BUFFER
AD9261
PHASE
LOCKED
LOOP
SERIAL
INTERFACE
OR
D15
D0
PLL_
LOCKED
CLK+
CLK–
DCO
AGND
SDIO SCLK CSB DGND
Figure 1.
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic.
The AD9261 operates on a 1.8 V analog supply and a 1.8 V
to 3.3 V digital supply, consuming 340 mW. The AD9261 is
available in a 48-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2. Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3. An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
4. An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
5. This part operates from a single 1.8 V analog power supply
and 1.8 V to 3.3 V output supply.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.

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AD9261* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD9261 Evaluation Board
Documentation
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-283: Sigma-Delta ADCs and DACs
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
Data Sheet
• AD9261: 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160
MSPS Continuous Time Sigma-Delta ADC Preliminary
Data Sheet
Reference Materials
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
• Understanding Continuous-Time, Discrete-Time Sigma-
Delta ADCs And Nyquist ADCs
Design Resources
• AD9261 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9261 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
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AD9261
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
DC Specifications ......................................................................... 3 
AC Specifications.......................................................................... 4 
Digital Decimation Filtering Characteristics............................ 4 
Digital Specifications ................................................................... 5 
Switching Specifications .............................................................. 6 
Absolute Maximum Ratings............................................................ 7 
Thermal Resistance ...................................................................... 7 
ESD Caution.................................................................................. 7 
Pin Configuration and Function Descriptions............................. 8 
REVISION HISTORY
4/10—Revision 0: Initial Version
Typical Performance Characteristics ..............................................9 
Equivalent Circuits......................................................................... 13 
Theory of Operation ...................................................................... 14 
Analog Input Considerations ................................................... 14 
Clock Input Considerations...................................................... 16 
Power Dissipation and Standby Mode .................................... 18 
Digital Engine ............................................................................. 19 
Digital Outputs ........................................................................... 21 
Timing ......................................................................................... 21 
Serial Port Interface (SPI).............................................................. 23 
Configuration Using the SPI..................................................... 23 
Hardware Interface..................................................................... 24 
Memory Map .................................................................................. 25 
Memory Map Definitions ......................................................... 25 
Outline Dimensions ....................................................................... 27 
Ordering Guide .......................................................................... 27 
Rev. 0 | Page 2 of 28

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AD9261
SPECIFICATIONS
DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ANALOG INPUT BANDWIDTH
ACCURACY
No Missing Codes
Offset Error
Gain Error
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
ANALOG INPUT
Input Span, VREF = 0.5 V
Common-Mode Voltage
Input Resistance
POWER SUPPLIES
Supply Voltage
AVDD
CVDD
DVDD
DRVDD
Supply Current
IAVDD2
ICVDD2 PLL Enabled
ICVDD2 PLL Disabled
IDVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
POWER CONSUMPTION
Sine Wave Input2 PLL Disabled
Sine Wave Input2 PLL Enabled
Power-Down Power
Standby Power2
Sleep Power
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min Typ
16
Max Unit
Bits
10 MHz
Guaranteed
±0.02
±0.15
±0.7 ±3.0
±1.5
% FSR
% FSR
LSB
±1.5
±50
490 500
510
ppm/°C
ppm/°C
mV
2 V p-p diff
1.7 1.8 1.9 V
1 kΩ
1.7 1.8 1.9 V
1.7 1.8 1.9 V
1.7 1.8 1.9 V
1.7 1.8 3.6 V
74 83 mA
57 654 mA
8.0 8.8 mA
100 108 mA
5.5 5.8 mA
10 mA
340 370 mW
425 465 mW
20 mW
7 mW
3 4 mW
1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted.
2 Measured with a low input frequency, full-scale sine wave.
Rev. 0 | Page 3 of 28

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AD9261
AC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 4.2 MHz
fIN = 8.4 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 4.2 MHz
fIN = 8.4 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 4.2 MHz
fIN = 8.4 MHz
NOISE SPECTRAL DENSITY (NSD)
AIN= −2 dBFS
AIN = −40 dBFS
NOISE FIGURE2
TWO-TONE SFDR
fIN1 = 2.1 MHz at −8 dBFS, fIN2 = 2.4 MHz at −8 dBFS
fIN1 = 3.6 MHz at −8 dBFS, fIN2 = 4.2 MHz at −8 dBFS
fIN1 = 7.2 MHz at −8 dBFS, fIN2 = 8.4 MHz at −8 dBFS
ANALOG INPUT BANDWIDTH
APERTURE JITTER
Temp
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
Min Typ
81 83
83
83
13.5
13.5
13.5
87
87
<120
−155
−156
15
93
92.5
92.5
Max Unit
dB
dB
dB
Bits
Bits
Bits
80 dBc
dBc
dBc
−153
−154.5
dB/Hz
dB/Hz
dB
dBc
dBc
dBc
10 MHz
1 ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Noise figure with respect to 50 Ω. AD9261 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition.
DIGITAL DECIMATION FILTERING CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
Pass-Band Transition
Pass-Band Ripple
Stop Band
Stop Band Attenuation
2.5 MHz BW
Min Typ
2.5
<0.1
3.75 MHz − fS/2
>85
5 MHZ BW
Max Min Typ
3.75 5
<0.1
6.5 MHz − fS/2
>85
10 MHz BW
Max Min Typ
6.5 10
<0.1
13 MHz − fS/2
>85
Max Unit
13 MHz
dB
MHz
dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. 0 | Page 4 of 28