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BCD DECADE/MODULO
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL COUNTERS
The SN54 / 74LS168 and SN54 / 74LS169 are fully synchronous 4-stage
up/down counters featuring a preset capability for programmable operation,
carry lookahead for easy cascading and a U/ D input to control the direction
of counting. The SN54 / 74LS168 counts in a BCD decade (8, 4, 2, 1)
sequence, while the SN54 / 74LS169 operates in a Modulo 16 binary
sequence. All state changes, whether in counting or parallel loading, are
initiated by the LOW-to-HIGH transition of the clock.
Low Power Dissipation 100 mW Typical
High-Speed Count Frequency 30 MHz Typical
Fully Synchronous Operation
Full Carry Lookahead for Easy Cascading
Single Up / Down Control Input
Positive Edge-Trigger Operation
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
16
TC
15
Q0
14
Q1
13
Q2
12
Q3
11
CET
10
PE
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
U/D
2
CP
3
P0
4
P1
5
P2
6
P3
78
CEP GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
CEP Count Enable Parallel (Active LOW) Input
0.5 U.L. 0.25 U.L.
CET Count Enable Trickle (Active LOW) Input
1.0 U.L.
0.5 U.L.
CP Clock Pulse (Active positive going edge) Input 0.5 U.L. 0.25 U.L.
PE Parallel Enable (Active LOW) Input
0.5 U.L. 0.25 U.L.
U/D Up-Down Count Control Input
0.5 U.L. 0.25 U.L.
P0–P3 Parallel Data Inputs
Q0–Q3 Flip-Flop Outputs
TC Terminal Count (Active LOW) Output
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS168
SN54/74LS169
BCD DECADE/ MODULO
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
93
4
56
1
7
10
2
PE
U/D
P0
P1
CEP
CET
P2 P3
TC
CP
Q0 Q1 Q2 Q3
15
14 13 12 11
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-302

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SN54/74LS168 SN54/74LS169
SN54/ 74LS168
UP / DOWN DECADE COUNTER
STATE DIAGRAMS
01234
0
SN54 / 74LS169
123
4
15
5
15
5
Count Up
14
6
Count Down
14
6
13
7
13
7
12 11 10
9
8
SN54 / 74LS168
UP: TC = Q0 Q3 (U / D)
DOWN: TC = Q0 Q1 Q2 Q3 (U / D)
12 11 10
9
8
SN54 / 74LS169
UP: TC = Q0 Q1 Q2 Q3 (U / D)
DOWN: TC = Q0 Q1 Q2 Q3 (U / D)
PE
CEP
CET
U/D
P0
LOGIC DIAGRAMS
SN54 / 74LS168
P1
P2
P3
TC
CP
CP
D
Q0
Q1
Q2
FAST AND LS TTL DATA
5-303
Q3

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PE
CEP
CET
U/D
P0
SN54/74LS168 SN54/74LS169
LOGIC DIAGRAMS (continued)
SN54 / 74LS169
P1
P2
P3
TC
CP
CP
D
Q0
Q1
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Q2
Q3
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
FAST AND LS TTL DATA
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SN54/74LS168 SN54/74LS169
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
54
VIL Input LOW Voltage
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.5 3.5
2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIH
V IOL = 8.0 mA per Truth Table
Input HIGH Current
Other Inputs
IIH CET Input
Other Input
CET Input
20 µA VCC = MAX, VIN = 2.7 V
40
0.1
0.2
mA VCC = MAX, VIN = 7.0 V
Input LOW Current
IIL Other Input
CET Input
– 0.4 mA VCC = MAX, VIN = 0.4 V
– 0.8
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
34
Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.
mA VCC = MAX
FUNCTIONAL DESCRIPTION
The SN54/74LS168 and SN54/74LS169 use edge-
triggered D-type flip-flops that have no constraints on
changing the control or data input signals in either state of the
Clock. The only requirement is that the various inputs attain
the desired state at least a set-up time before the rising edge of
the clock and remain valid for the recommended hold time
thereafter.
The parallel load operation takes precedence over the other
operations, as indicated in the Mode Select Table. When PE is
LOW, the data on the P0 – P3 inputs enters the flip-flops on the
next rising edge of the Clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH. The
U/D input then determines the direction of counting.
The Terminal Count (TC) output is normally HIGH and goes
LOW, provided that CET is LOW, when a counter reaches zero
in the COUNT DOWN mode or reaches 15 (9 for the
SN54/74LS168) in the COUNT UP mode. The TC output state
is not a function of the Count Enable Parallel (CEP) input level.
The TC output of the SN54/74LS168 decade counter can also
be LOW in the illegal states 11, 13 and 15, which can occur
when power is turned on or via parallel loading. If illegal state
occurs, the SN54/74LS168 will return to the legitimate
sequence within two counts. Since the TC signal is derived by
decoding the flip-flop states, there exists the possibility of
decoding spikes on TC. For this reason the use of TC as a
clock signal is not recommended.
MODE SELECT TABLE
PE
CEP
CET
U/D
Action on Rising Clock Edge
L X X X Load (Pn Qn)
H L L H Count Up (increment)
H L L L Count Down (decrement)
H H X X No Change (Hold)
H X H X No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
FAST AND LS TTL DATA
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SN54/74LS168 SN54/74LS169
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
Maximum Clock Frequency
25 32
tPLH
tPHL
Propagation Delay,
Clock to TC
23 35
23 35
tPLH
tPHL
Propagation Delay,
Clock to any Q
13 20
15 23
tPLH
tPHL
Propagation Delay,
CET to TC
15 20
15 20
tPLH
tPHL
Propagation Delay,
U / D to TC
17 25
19 29
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
ts
ts
th
Parameter
Clock Pulse Width
Setup Time,
Data or Enable
Setup Time
PE
Setup Time
U/D
Hold Time
Any Input
Limits
Min Typ Max
25
20
25
30
0
Unit
MHz
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-306