FPF1320.pdf 데이터시트 (총 16 페이지) - 파일 다운로드 FPF1320 데이타시트 다운로드

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September 2013
FPF1320 / FPF1321
IntelliMAX™ Dual-Input Single-Output Advanced Power
Switch with True Reverse-Current Blocking
Features
DISO Load Switches
Input Supply Operating Range: 1.5 V ~ 5.5 V
RON 50 mat VIN=3.3 V Per Channel (Typical)
True Reverse-Current Blocking (TRCB)
Fixed Slew Rate Controlled 130 µs for < 1 µF COUT
ISW: 1.5 A Per Channel (Maximum)
Quick Discharge Feature on FPF1321
Logic CMOS IO Meets JESD76 Standard for GPIO
Interface and Related Power Supply Requirements
ESD Protected:
- Human Body Model: >6 kV
- Charged Device Model: >1.5 kV
- IEC 61000-4-2 Air Discharge: >15 kV
- IEC 61000-4-2 Contact Discharge: >8 kV
Applications
Smart phones / Tablet PCs
Portable Devices
Near Field Communication (NFC) Capable
SIM Card Power Supply
Description
The FPF1320/21 is a Dual-Input Single-Output (DISO)
load switch consisting of two sets of slew-rate
controlled, low on-resistance, P-channel MOSFET
switches and integrated analog features. The slew-rate-
controlled turn-on characteristic prevents inrush current
and the resulting excessive voltage droop on the power
rails. The input voltage range operates from 1.5 V to
5.5 V to align with the requirements of low-voltage
portable device power rails. FPF1320/21 performs
seamless power-source transitions between two input
power rails using the SEL pin with advanced break-
before-make operation.
FPF1320/21 has a TRCB function to block unwanted
reverse current from output to input during ON/OFF
states. The switch is controlled by logic inputs of the
SEL and EN pins, which are capable of interfacing
directly with low-voltage control signals (GPIO).
FPF1321 has 65 on-chip load resistor for output quick
discharge when EN is LOW.
FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP,
6-bump, with 0.5 mm pitch. FPF1321B is available in
1.0 mm x 1.5 mm WLCSP, 6-bump, 0.5 mm pitch with
backside laminate.
Ordering Information
Part Number
Top
Mark
Switch Per
Channel Channel (Typ.)
at 3.3 VIN
Reverse
Current
Blocking
Output Rise
Discharge Time (tR)
Package
FPF1320UCX QS DISO
FPF1321UCX QT DISO
50 m
50 m
Yes NA 130 µs 1.0 mm X 1.5 mm
Wafer-Level Chip-
Scale Package
Yes
65
130 µs
(WLCSP) 6-Bumps,
0.5 mm Pitch
FPF1321BUCX QT DISO
50 m
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
1.0 mm X 1.5 mm
Wafer-Level Chip-
Yes
65
130 µs
Scale Package
(WLCSP) 6-Bumps,
0.5 mm Pitch with
Backside Laminate
www.fairchildsemi.com

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Application Diagram
Block Diagram
Figure 1. Typical Application
Figure 2. Functional Block Diagram (Output Discharge Path for FPF1321 Only)
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
2
www.fairchildsemi.com

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Pin Configuration
Figure 3. Pin Configuration in Package View with Pin 1 Indicator
EN
A1
SEL
B1
GND
C1
VIN A
A2
VOUT
B2
VIN B
C2
VIN A
A2
VOUT
B2
VIN B
C2
EN
A1
SEL
B1
GND
C1
Pin Description
Pin #
A1
Name
EN
B1 SEL
A2 VINA
B2 VOUT
C1 GND
C2 VINB
Top View
Bottom View
Figure 4. Pin Assignments
Description
Enable input. Active HIGH. There is an internal pull-down resistor at the EN pin.
Input power selection inputs. See Table 1. There are internal pull-down resistors at the
SEL pins.
Supply Input. Input to the power switch A.
Switch output
Ground
Supply Input. Input to power switch B.
Table 1.
SEL
LOW
HIGH
Truth Table
EN Switch A
HIGH
ON
HIGH
OFF
X LOW
OFF
Switch B
OFF
ON
OFF
VOUT
VINA
VINB
Floating for FPF1320
GND for FPF1321
Status
VINA Selected
VINB Selected
Both Switches are OFF
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
3
www.fairchildsemi.com

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Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameters
VIN
ISW
PD
TSTG
VINA, VINB, VSEL, VEN, VOUT to GND
Maximum Continuous Switch Current per Channel
Total Power Dissipation at TA=25°C
Operating and Storage Junction Temperature
ΘJA
Thermal Resistance, Junction-to-Ambient
(1 in.2 Pad of 2-oz. Copper)
Human Body Model, JESD22-A114
ESD
Electrostatic Discharge
Capability
Charged Device Model, JESD22-C101
Air Discharge (VINA, VINB to GND),
IEC61000-4-2 System Level
Contact Discharge (VINA, VINB to
GND), IEC61000-4-2 System Level
Notes:
1. Measured using 2S2P JEDEC std. PCB.
2. Measured using 2S2P JEDEC PCB cold-plate method.
Min.
-0.3
-65
6.0
1.5
15.0
8.0
Max.
6
1.5
1.2
150
85(1)
110(2)
Unit
V
A
W
°C
°C/W
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VIN
TA
Parameters
Input Voltage on VINA, VINB
Ambient Operating Temperature
Min.
1.5
-40
Max.
5.5
85
Unit
V
°C
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
4
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Electrical Characteristics
VINA=VINB=1.5 to 5.5 V, TA=-40 to 85°C unless otherwise noted. Typical values are at VINA=VINB=3.3 V and TA=25°C.
Symbol
Parameters
Condition
Basic Operation
VINA, VINB
ISD
Input Voltage
Shutdown Current
IQ Quiescent Current
RON On-Resistance
VIH
SEL, EN Input Logic High
Voltage
SEL=HIGH or LOW, EN=GND,
VOUT=GND, VINA=VINB=5.5 V
IOUT=0mA, SEL=HIGH or LOW,
EN=HIGH, VINA=VINB=5.5 V
VINA=VINB=5.5 V, IOUT=200 mA,
TA=25°C
VINA=VINB=3.3 V, IOUT=200 mA,
TA=25°C
VINA=VINB=1.8 V, IOUT=200 mA,
TA=25°C to 85°C
VINA=VINB=1.5 V, IOUT=200 mA,
TA=25°C
VINA, VINB=1.5 V – 5.5 V
SEL, EN Input Logic Low
Voltage
VINA, VINB=1.8 V – 5.5 V
VIL
SEL, EN Input Logic Low
Voltage
VINA, VINB=1.5 V – 1.8 V
VDROOP_OUT
Output Voltage Droop while
Channel Switching from
Higher Input Voltage Lower
Input Voltage(3)
VINA=3.3 V, VINB=5 V, Switching from
VINA VINB, RL=150 , COUT=1 µF
ISEL/IEN
Input Leakage at SEL and
EN Pin
RSEL_PD/REN_PD
Pull-Down Resistance at
SEL or EN Pin
RPD
Output Pull-Down
Resistance
True Reverse Current Blocking
SEL=HIGH or LOW, EN=GND,
IFORCE=20 mA, TA=25°C, FPF1321
VT_RCB
VR_RCB
RCB Protection Trip Point
RCB Protection Release
Trip Point
VOUT - VINA or VINB
VINA or VINB -VOUT
IRCB
VINA or VINB Current During VOUT=5.5 V, VINA or VINB=Short to
RCB
GND
tRCB_ON
RCB Response Time when
Device is ON(3)
VINA or VINB=5 V, VOUTVINA,B=100 mV
Min. Typ. Max. Unit
1.5 5.5 V
5 µA
12 22 μA
42 60
50
m
80
170
1.15 V
0.65 V
0.60
100 mV
1.2 μA
7 M
65
45 mV
25 mV
9 15 μA
5 µs
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
5
www.fairchildsemi.com