TC55416P-35.pdf 데이터시트 (총 5 페이지) - 파일 다운로드 TC55416P-35 데이타시트 다운로드

No Preview Available !

TOSHIBA MOS MEMORY PRODUCT
16,384 WORD X 4 BIT CMOS STATIC RAM
SILICON GATE CMOS
TC55416P-35
TC55416P-45
DESCRIPTION
The TC55416P is a 65,536 bit high speed static random access memory organized as 16,384 words by 4 bits
using CMOS technology, and operated from a single 5-volt supply. Toshiba's high performance device technology
provides both high speed and low power features with a maximum access time of 35ns/45ns and maximum
operating current of 80mA/60mA at minimum cycle time.
The TC55416P also features an automatic stand-by mode. When deselected by Chip Enable (CE), the operating
current is reduced to lOrnA.
The TC55416P is suitable for use in cache memory and high speed storage, where high speed/high density are
required.
The TC55416P is molded in a 22 pin standard plastic package with 0.3 inch width for high density assembly.
The TC55416P is fabricated with ion implanted CMOS silicon gate MOS technology for high performance and
high reliability.
I'FEATURES
Fast access time
TC554l6P-35 35ns (Max.)
TC554l6P-45 45nS (Max.)
Low power dissipation Operation TC554l6P-35 80mA (Max.)
TC554l6P-45 60mA (Max.)
Standby
lOrnA (Max.)
. 5V single power supply
. Fully static operation
Directly TTL compatible All Input and Output
Package
22 pins standard plastic package, 300 mil width.
I'PIN CONNECTION
I'BLOCK DIAGRAM
A5
AO
CE
GND
(300mll DIP)
vDD
Ag
AIO
All
AJ2
A13
I/Ol
I/02
I/03
I/O 4.
WE
IIPIN NAMES
• Ao-A13
1/01-1/04
CE
WE
Von
GND
Address Inputs
Data Input/Output
Chip Enable Input
Write Enable Input
Power (+5V)
Ground
CE
A6
A7
AS
A9
A10
All
A12
A13
I/Ol
I/02
I/03
I/04
----OVDD
----oOND
CE~~~~~~~~~~~~~
WE
- C-69 -

No Preview Available !

TliDD41 UP-3D
TC55416P-45
~1AXIMUM RATINGS
SYMEOL
VDn
VIN
VOUT
PD
Tsolder
Tstg
Topr
ITEM
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Soldering Temperature
Storage Temperature
Operating Temperature
D.C. RECOMMENDED OPERATING CONDITIONS
SYMBOL
Von
VIH
VIL
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
RATING
-0.3~7.0
-2.0-7.0
-0. 5-VDo+0. 5
650
260·10
-65-150
0-70 •..
UNIT
V
.V
V
mW
°C·sec
°c
°c
MIN.
4.5
2.2
-0.3
TYP.
MAX. UNIT
5.0 5.5
V
- VOo+O.3 V
- 0.8 V
D.C. and OPERATING CHARACTERISTICS (Ta=0-70°C, VDO=5V±10%)
SYMBOL
IlL
IOH
IOL
ILO
IDOO
IDDSI
IDDS2
PARAMETER
Input Leakage Current
Output High Current
Output Low Current
Output Leakage Current
Operating Current
Standby Current
TEST CONDITION
VIN=O-VOD
VOH=2.4V
VOL=0.4V
CE=VIH or WE=VIL
VOUT=O-VOD-
VOD=5,~V
tcyclc=Min cycle
-35
CE=VIL
Other Input=VIH/vIL
-45
VOO=5.5V, tcycle=Min cycle
CE=VIH, Other Input=VIH/VIL
CE=VOD-0.2V
Other Input=VDO-0.2V or 0.2V
MIN.
-
-4
8
-
-
-
-
-
TYP. MAX.
- ±1.0
--
--
- ±1.0
- 80
- 60
- 20
-1
UNIT
~A
rnA
rnA
~A
rnA
rnA
CAPACITANCE (Ta=25°C)
SYMBOL
PARAMETER
TEST CONDITION
CIN Input Capacitance
VIN=GND
Com Output Capacitance
VOUT-GND
Note: This parameter periodically sampled is not 100% tested.
MAX.
10
10
UNIT
pF
pF
- C-70 -

No Preview Available !

TC5541 Ii P-35
TC55416 P-45
A.C. CHARACTERISTICS (Ta-0-70°C, VDD=5V±10%)
Read Cycle
SYMBOL
PARAMETER
tRC
tACC
tco
tCOE
teoD
tOH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low-Z
Chip Enable to Output in High-Z
Output Data Hold Time
Write Cycle
SYMBOL
PARAMETER
twe
twp
tcw
tAS
tWR
tODW
tOEW
tDS
tDH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Set Up Time
Write Recovery Time
WE to Output High-Z
WE to Output Low-Z
Data Set Up Time
Data Hold Time
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing
Reference Levels
Output Load
0.6V, 2.4V
5ns
O.8V, 2.0V
See Fig.l
TCS54l6P-35
MIN. MAX.
35 -
- 35
- 35
0-
- 15
5-
TC55416P-45
MIN. MAX.
45 -
- 45
- 45
0-
.-... 20
5-
UNIT
ns
ns
ns
ns
ns
ns
TC554l6P-35
MIN. MAX.
35 -
30 -
30 -
0-
0-
- 15
0-
15 -
0-
TC55416P-45
MIN. MAX.
45 -
35 -
35 -
0-
0-
- 15
0-
20 -
0-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
I/O PIN 0-_--.-4
Fig.l OUTPUT LOAD
Note: In all condition, tCOD max is less than tCOE min both for a given device and
from device to device.
- C-71 -

No Preview Available !

TC:J:J41Ii P"3:J
TC55416P-45
TIMING WAVEFORMS
READ CYCLE(l)
ADDRESS
DOUT
WRITE CYCLE 1 (WE Controlled Write)
ADDRESS
twc
tcw
DOUT
DIN
WRITE CYCLE 2 (CE Controlled Write)
ADDRESS
HIGH IllPEDANCE
tDS
_~_D_A_T_A _I_N________~,_________
twc
tcw
DoUT
HIGH
Note: 1. WE is High for Read Cycle.
2. Assuming that CE Low transition occurs coincident with or after WE
Low transition, Outputs remain in a high impedance state.
3 •. Assuming that ~ High transition occurs coincident with or prior to WE
High transition, Outputs remain in a high impedance state.
4. The Operating temperature (Ta) is guaranteed with transverse air flow
exceeding 400 linear feet per minute.
- C-72 -

No Preview Available !

OUTLINE DRAWINGS
~U
~[[::::::::::I
1 II
TC55416P-35
TC55416P-45
Unit in mm
;z:
:i 2.54.:::0.25
0.5:::0.0'1
10
10 (Note)
d 1.4.:::0.07
Note:
Each lead pitch is 2.54mm.
All leads are located within O.25mm of the true longitudinal positiun
with respect to No.1 and No.22 leads.
- C-73 -