ISL62875.pdf 데이터시트 (총 22 페이지) - 파일 다운로드 ISL62875 데이타시트 다운로드

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PWM DC/DC Controller with VID Inputs for
Portable GPU Core-Voltage Regulator
ISL62875
The ISL62875 is a Single-Phase Synchronous-Buck
PWM voltage regulator featuring Intersil’s Robust Ripple
Regulator (R3) Technology™. The wide 3.3V to 25V
input voltage range is ideal for systems that run on
battery or AC-adapter power sources. The ISL62875 is a
low-cost solution for applications requiring dynamically
selected slew-rate controlled output voltages. The
soft-start and dynamic setpoint slew-rates are capacitor
programmed. Voltage identification logic-inputs select
four resistor-programmed setpoint reference voltages
that directly set the output voltage of the converter
between 0.5V to 1.5V, and up to 3.3V using a feedback
voltage divider. Robust integrated MOSFET drivers and
Schottky bootstrap diode reduce the implementation
area and component cost.
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency and hysteretic PWM control. The
PWM frequency is 500kHz during static operation,
becoming variable during changes in load, setpoint
voltage, and input voltage when changing between
battery and AC-adapter power. The modulators ability to
change the PWM switching frequency during these
events in conjunction with external loop compensation
produces superior transient response. For maximum
efficiency, the converter automatically enters diode-
emulation mode (DEM) during light-load conditions such
as system standby.
Features
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 3.3V
• Output Load up to 30A
• Extremely Flexible Output Voltage Programmability
- 2-Bit VID Selects Four Independent Setpoint
Voltages
- Simple Resistor Programming of Setpoint Voltages
- Accepts External Setpoint Reference such as DAC
• ±0.75% System Accuracy: -10°C to +100°C
• Fixed 500kHz PWM Frequency in Continuous
Conduction
• Integrated High-current MOSFET Drivers and
Schottky Boot-Strap Diode for Optimal Efficiency
Applications*(see page 21)
• Mobile PC GPU Core Power
• Mobile PC I/O Controller Hub (ICH) VCC Rail
• Tablet PCs/Slates and Netbooks
• Hand-Held Portable Instruments
Related Literature*(see page 21)
• TB389 “PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages”
Typical Application
+5V
GPIO
CPVCC
1
2
PGND
3
GND
4
EN
5 VID1
6 VID0
7 SREF
8 SET0
9 SET1
20
19
VCC
18
BOOT
17
UGATE
PHASE 16
14
OCSET
13
VO
12
FB
10 11 VCC
RSET1 RSET2 RSET3
GPIO
CVCC
QHS
CBOOT
QLS
VIN
3.3V TO 25V
CIN
LO
COCSET
VOUT
0.5V TO 3.3V
COUT
RCOMP
CCOMP
RO
RFB
FN6905.1
September 18, 2009
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC
Copyright Intersil Americas LLC 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Application Schematics
+5V
RVCC
ISL62875
GPIO
CPVCC
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
2
3
4
5
6
7
8
9
RSET1 RSET2 RSET3
19 VCC
18 BOOT
17 UGATE
16 PHASE
15 NC
14 OCSET
13 VO
12 FB
VCC
CVCC
CBOOT
QHS
QLS
LO
COCSET
RCOMP
CCOMP
RO
GPIO
RFB
VIN
3.3V TO 25V
CINC
CINB
VOUT
0.5V TO 3.3V
COC
COB
FIGURE 1. ISL62875 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT
SENSE
+5V
GPIO
RVCC
CPVCC
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
2
3
4
5
6
7
8
9
RSET1 RSET2 RSET3
19 VCC
18 BOOT
17 UGATE
16 PHASE
15 NC
14 OCSET
13 VO
12 FB
VCC
CVCC
CBOOT
QHS
LO
QLS
VIN
3.3V TO 25V
CINC
CINB
RSNS
COCSET
VOUT
0.5V TO 3.3V
COC
COB
RCOMP
CCOMP
RO
GPIO
RFB
FIGURE 2. ISL62875 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR
CURRENT SENSE
2 September 18, 2009
FN6905.1

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ISL62875
Application Schematics (Continued)
RVCC
+5V
CPVCC
GPIO
EXT_REF
VCC
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
2
3
4
5
6
7
8
9
19 VCC
18 BOOT
17 UGATE
16 PHASE
15 NC
14 OCSET
13 VO
12 FB
CVCC
CBOOT
RCOMP
QHS
QLS
LO
COCSET
CCOMP
RO
VIN
3.3V TO 25V
CINC
CINB
VOUT
0.5V TO 3.3V
COC
COB
GPIO
RFB
FIGURE 3. ISL62875 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE
3 September 18, 2009
FN6905.1

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Block Diagram
FB
SREF
SET0
SET1
SET2
VID1
VID0
GND
EN VCC
POR
100k
EA
VCOMP
100pF
VSET
SW0
SW1
SW2
SW3
FAULT
RUN
H
L
VW IN
PWM
RUN
DRIVER
OTP
SHOOT-THROUGH
PROTECTION
PWM RUN DRIVER
gmVIN
VCC
Cr
VR
gmVO
VID DECODER
INT
500mV
EXT
SW4
VREF
FB
UVP
FAULT
OCP
FIGURE 4. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL62875
IOCSET
10µA
BOOT
UGATE
PHASE
PVCC
LGATE
PGND
VO
OCSET
PGOOD

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Pin Configuration
ISL62875
ISL62875
(20 LD 3.2X1.8 ΜTQFN)
TOP VIEW
PGND 2
GND 3
EN 4
VID1 5
VID0 6
SREF 7
SET0 8
SET1 9
19 VCC
18 BOOT
17 UGATE
16 PHASE
15 NC
14 OCSET
13 VO
12 FB
ISL62875 Functional Pin Descriptions
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
SYMBOL
LGATE
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
SET2
PGOOD
FB
VO
DESCRIPTION
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of
the converter.
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
IC ground for bias supply and signal reference.
Enable input for the IC. Pulling EN above the VENTHR rising threshold voltage initializes the
soft-start sequence.
Logic input for setpoint voltage selector. Use in conjunction with the VID0 pin to select among four
setpoint reference voltages.
Logic input for setpoint voltage selector. Use in conjunction with the VID1 pin to select among
four setpoint reference voltages. External reference input when enabled by connecting the
SET0 pin to the VCC pin.
Soft-start and voltage slew-rate programming capacitor input. Setpoint reference voltage
programming resistor input. Connects internally to the inverting input of the VSET voltage
setpoint amplifier.
Voltage set-point programming resistor input.
Voltage set-point programming resistor input.
Voltage set-point programming resistor input.
Power-good open-drain indicator output. This pin changes to high impedance when the
converter is able to supply regulated voltage. The pull-down resistance between the PGOOD
pin and the GND pin identifies which protective fault has shut down the regulator.
Voltage feedback sense input. Connects internally to the inverting input of the control-loop
error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage
on the SREF pin. The control loop compensation network connects between the FB pin and the
converter output.
Output voltage sense input for the R3 modulator. The VO pin also serves as the reference input
for the overcurrent detection circuit.
5 September 18, 2009
FN6905.1